Main

Advanced

Security

Power

Boot

Exit

System Memory Speed [Not Detected]

Total Memory [Not Detected]

SATA Port 0 Not Present

SATA Port 1 Not Present

SATA Port 2 Not Present

SATA Port 3 Not Present

SATA Port 4 Not Present

SATA Port 5 Not Present

SATA Port 6 Not Present

SATA Port 7 Not Present

OffBoard SATA Controller Configuration

OffBoard NVMe Controller Configuration

[Not Detected]

ME FW Version N/A

System Memory: 640KB

Extended Memory: N/A

DIMM#0 Not Present

DIMM#1 Not Present

DIMM#2 Not Present

DIMM#3 Not Present

Memory Frequency N/A

Channel A

Size N/A

Channel B

Size N/A

Number of Processors xCore(s) / yThread(s)

Frequency N/A

L1 Data Cache N/A

L1 Instruction Cache N/A

L2 Cache N/A

L3 Cache N/A

Serial Number: OEM Serial Type 1

Serial Number: OEM Serial Type 2

MB Series: N/A

Brand: BANGHO

BIOS Version: N/A

KBC/EC Firmware Revision: N/A

VGA Card: N/A

VBIOS Revision: N/A

VBIOS Build Date: N/A

MAC Address: N/A

Clevo SHOW SETUP ITEM Settings

Clevo SETUP ITEM CONFIG Settings

Clevo SETUP ITEM LOGO Settings

Clevo SETUP ITEM CC3.0 Settings

Boot Configuration

Peripheral Configuration

SATA Configuration

USB Configuration

Chipset Configuration

Debug Settings

PCI Subsystem Settings

ACPI Table/Features Control

CPU Configuration

Connectivity Configuration

Power & Performance

OverClocking Performance Menu

Memory Configuration

System Agent (SA) Configuration

PCIE Configuration

PCH-IO Configuration

PCH-FW Configuration

Thermal Configuration

Platform Settings

ACPI D3Cold settings

PCH BCLK Configuration

Rework Configuration

Advanced Chipset Control

SATA Mode:

Determines how SATA controller(s) operate.

Boot Logo:

Enables/Disables boot logo

Power On Boot Beep:

Power On Boot Beep Control

Battery Low Alarm Beep:

Battery Low Alarm Beep Control

Firmware Configuration

Firmware Configuration options. NOTE:Ignore Policy Update(STR_FW_CONFIG_DEFAULT_VALUE) is to skip policy update and will ONLY WORK ON A PLATFORM.

Current TPM Device

Current TPM Device: TPM1.2, or TPM2.0.

TPM Operation

Enable/Disable TPM Function. This option will automatically return to No-Operation.

TPM Active PCR Hash Algorithm

TPM Hardware Supported Hash Algorithm

BIOS Supported Hash Algorithm

TrEE Protocol Version

TrEE Protocol Version: 1.0 or 1.1

PCR Bank: SHA1 Enabled

TCG2 Request PCR Bank: SHA1

PCR Bank: SHA256 Enabled

TCG2 Request PCR Bank: SHA256

PCR Bank: SHA384 Enabled

TCG2 Request PCR Bank: SHA384

PCR Bank: SHA512 Enabled

TCG2 Request PCR Bank: SHA512

PCR Bank: SM3_256 Enabled

TCG2 Request PCR Bank: SM3_256

Enabled

Supervisor Password Not Installed

User Password Not Installed

User Access Level

Limited:Only limited fields can be changed. No Access:Prevent User access to InsydeH2O Setup.View Only:Access to InsydeH2O Setup allowed but the fields cannot be changed.Full:Any field can be changed except the Supervisor password.

Set Supervisor Password

Old password

Please input old password to make chage work

New Password

Install or Change the password and the length of password must be greater than one character.

Confirm Password

Set User Password

Old password

Please input old password to make chage work

New Password

Install or Change the password and the length of password must be greater than one character.

Confirm Password

Clear User Password

Power on Password

Enable:System will ask input password on post time. Disable:System will ask input password when go to Setup Utility

TPM Configuration

Set All Hdd Password

Old password

Please input old password to make chage work

New Password

Set all HDD password and suggest the length of password greater than one character. This item can be displayed when any security mode of HDD is not Lock. This item can be used for ATA Password Security; TCG Opal Security is not supported by design.

Confirm Password

Set All Master Hdd Password

Old password

Please input old password to make chage work

New Password

Set all master HDD password and suggest the length of password greater than one character. This item can be used when all of HDDs are set HDD password. This item can be used for ATA Password Security; TCG Opal Security is not supported by design.

Confirm Password

Storage Password Setup Page

ACPI S1

Enable/Disable ACPI S1/S3 Sleep state

ACPI S3

Enable/Disable ACPI S1/S3 Sleep state

Wake on PME

Determines the action taken when the system power is off and a PCI Power Management Enable wake up event occurs.

Wake on Modem Ring

Determines the action taken when the system power is off and a modem connected to the serial port is ringing.

Auto Wake on S5

Auto wake on S5, By Day of Month or Fixed time of every day

Wake on S5 Time

This is the help for the hour, minute, second field. Valid range is from 0 to 23, 0 to 59, 0 to 59. INCREASE/REDUCE : +/-.

Day of Month

This is the help for the day field. Valid range is from 1 to 31. (Error checking will be done against month/day/year combinations that are not suppo-ported. INCREASE/REDUCE : +/-.

S5 Long Run Test

Enable : force to enable RTC S5 wake up, even if OS disables it. Support ipwrtest to do RTC S5 wakeup.

H2OUve Configuration

Quick Boot

Allows InsydeH2O to skip certain tests while booting. This will decrease the time needed to boot the system.

Quiet Boot

Disables or enables booting in Text Mode.

Power Up In Standby Support

Disable or enable Power Up In Standby Support. The PUIS feature set allows devices to be powered-up into the Standby power management state to minimize inrush current at power-up and to allow the host to sequence the spin-up of devices.

Storage PCI Option Rom access right Support

Disable or enable storage PCI option rom acceess right. This feature will enable or disable storage PCI option rom being load and dispatched.

Add Boot Options

Position in Boot Order for Shell,Network and Removables

ACPI Selection

Select booting to Acpi3.0/Acpi4.0/Acpi5.0/Acpi6.0/Acpi6.1/Acpi6.2/Acpi6.3

EFI Device First

Determine EFI device first or legacy device first. If enable, it is EFI device first. If disable, it is Legacy device first.

USB Hot Key Support

Enable/Disable to support USB hot key while booting. This will decrease the time needed to boot the system.

Timeout

The number of seconds that the firmware will wait before booting the original default boot selection.

Automatic Failover

Enable: if boot to default device fail, it will directly try to boot next device. Disable: if boot to default device fail, it will pop warning message then go into firmware UI.

EFI

Legacy

UEFI Setting

BootTypeOrder

Exit Saving Changes

Exit system setup and save your changes.

Save Change Without Exit

Save your changes and without exiting system.

Exit Discarding Changes

Exit system setup and without saving your changes.

Discard Changes

System Memory Speed [Not Detected]

Total Memory [Not Detected]

SATA Port 0 Not Present

SATA Port 1 Not Present

SATA Port 2 Not Present

SATA Port 3 Not Present

SATA Port 4 Not Present

SATA Port 5 Not Present

SATA Port 6 Not Present

SATA Port 7 Not Present

OffBoard SATA Controller Configuration

OffBoard NVMe Controller Configuration

[Not Detected]

ME FW Version N/A

System Memory: 640KB

Extended Memory: N/A

DIMM#0 Not Present

DIMM#1 Not Present

DIMM#2 Not Present

DIMM#3 Not Present

Memory Frequency N/A

Channel A

Size N/A

Channel B

Size N/A

Number of Processors xCore(s) / yThread(s)

Frequency N/A

L1 Data Cache N/A

L1 Instruction Cache N/A

L2 Cache N/A

L3 Cache N/A

Serial Number: OEM Serial Type 1

Serial Number: OEM Serial Type 2

MB Series: N/A

Brand: BANGHO

BIOS Version: N/A

KBC/EC Firmware Revision: N/A

VGA Card: N/A

VBIOS Revision: N/A

VBIOS Build Date: N/A

MAC Address: N/A

SATA Port 0

LBA Format

Total Sectors:

Maximum Capacity:

Multi-Sector Transfers:

Transfer Mode:

Ultra DMA Mode:

SATA Port 1

LBA Format

Total Sectors:

Maximum Capacity:

Multi-Sector Transfers:

Transfer Mode:

Ultra DMA Mode:

SATA Port 2

LBA Format

Total Sectors:

Maximum Capacity:

Multi-Sector Transfers:

Transfer Mode:

Ultra DMA Mode:

SATA Port 3

LBA Format

Total Sectors:

Maximum Capacity:

Multi-Sector Transfers:

Transfer Mode:

Ultra DMA Mode:

SATA Port 4

LBA Format

Total Sectors:

Maximum Capacity:

Multi-Sector Transfers:

Transfer Mode:

Ultra DMA Mode:

SATA Port 5

LBA Format

Total Sectors:

Maximum Capacity:

Multi-Sector Transfers:

Transfer Mode:

Ultra DMA Mode:

SATA Port 6

LBA Format

Total Sectors:

Maximum Capacity:

Multi-Sector Transfers:

Transfer Mode:

Ultra DMA Mode:

SATA Port 7

LBA Format

Total Sectors:

Maximum Capacity:

Multi-Sector Transfers:

Transfer Mode:

Ultra DMA Mode:

OffBoard SATA Controller Configuration

OffBoard NVMe Controller Configuration

Clevo SHOW SETUP ITEM Settings

Clevo SETUP ITEM CONFIG Settings

Clevo SETUP ITEM LOGO Settings

Clevo SETUP ITEM CC3.0 Settings

Boot Configuration

Peripheral Configuration

SATA Configuration

USB Configuration

Chipset Configuration

Debug Settings

PCI Subsystem Settings

ACPI Table/Features Control

CPU Configuration

Connectivity Configuration

Power & Performance

OverClocking Performance Menu

Memory Configuration

System Agent (SA) Configuration

PCIE Configuration

PCH-IO Configuration

PCH-FW Configuration

Thermal Configuration

Platform Settings

ACPI D3Cold settings

PCH BCLK Configuration

Rework Configuration

Advanced Chipset Control

SATA Mode:

Determines how SATA controller(s) operate.

Boot Logo:

Enables/Disables boot logo

Power On Boot Beep:

Power On Boot Beep Control

Battery Low Alarm Beep:

Battery Low Alarm Beep Control

Firmware Configuration

Firmware Configuration options. NOTE:Ignore Policy Update(STR_FW_CONFIG_DEFAULT_VALUE) is to skip policy update and will ONLY WORK ON A PLATFORM.

PCI Configuration

PCI Slot3 IRQ Priority

Manual IRQ selection does not garantee PCI slot device will be configured with choice because PnP ISA Cards (if present) are assigned the available resources before PCI device.

PCI Slot4 IRQ Priority

Manual IRQ selection does not garantee PCI slot device will be configured with choice because PnP ISA Cards (if present) are assigned the available resources before PCI device.

Boot Configuration

Numlock

Selects Power-on state for Numlock

Peripheral Configuration

Serial Port A

Configure Serial port A using options : [Disable] No Configuration [Enable] User Configuration [Auto] EFI/OS chooses configuration

Base I/O Address

Interrupt

Infrared Port

Configure Infrared port using options : [Disable] No Configuration [Enable] User Configuration [Auto] EFI/OS chooses configuration

Mode

Set the mode for the parallel port using options

Base I/O Address

Interrupt

DMA Channel

High Speed

Set FIR to High speed mode or normal speed mode

SATA Configuration

AHCI Option ROM Support

If AHCI option ROM set disable ,the system can only detect port 0 to port 3.If AHCI option ROM set enable ,the system can detect all port.

Serial ATA Port 0

Serial ATA Port 1

Serial ATA Port 2

Serial ATA Port 3

Serial ATA Port 4

Serial ATA Port 5

Serial ATA Port 6

Serial ATA Port 7

Serial ATA Port 1

Serial ATA Port 3

Serial ATA Port 5

Serial ATA Port 7

USB Configuration

USB BIOS Support

USB keyboard/mouse/storage support under UEFI environment

USB BIOS Support

USB keyboard/mouse/storage support under UEFI and DOS environment. It will supporting UEFI environment only if set to UEFI Only

Usb Legacy SMI bit Clean

Clean Usb Legacy SMI bit for xHCI and EHCI

Chipset Configuration

Setup Warning:

Setting items on this screen to incorrect values

may cause your system to malfunction!

Platform Trust Technology

Enable/Disable Platform Trust Technology.

ACPI Table/Features Control

ACPI Settings

FACP - RTC S4 Wakeup

Value only for ACPI. Enable/Disable for S4 Wakeup from RTC

APIC - IO APIC Mode

This item is valid only for WIN2k and WINXP.Also,a fresh install of the OS must occur when APIC Mode is desired.Test the IO ACPI by setting item to Enable.The APIC Table will then be pointed to by the RSDT,the Local APIC will be initialized,and the proper enable bits will be set in ICH4M

Debug Settings

Kernel Debug Serial Port

Select Kernel Debug Port and report in ACPI DBG2 table

Kernel Debug Patch

Enable/Disable Kernel Debug Patch

Platform Debug Consent

To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type. Enabling this BIOS option will override other debug-related BIOS options. Manual: Do not use Platform Debug Consent to override other debug-relevant policies, but the user must set each debug option manually, aimed at advanced users. Note: DCI OOB (aka BSSB) uses CCA probe

Advanced Debug Settings

USB3 Type-C UFP2DFP Kernel/Platform Debug Support

This BIOS option enables kernel and platform debug for USB3 interface over a UFP Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting

DCI Enable

Determine if to enable DCI debug from host

USB DbC Enable Mode

Disabled:Clear both USB2/3DBCEN USB2:Set USB2DBCEN USB3:Set USB3DBCEN Both:Set both USB2/3DBCEN No Change:Comply with HW value

Enable DCI ModPHY Power Gate

Enable ModPHY Power Gate when DCI is enabled

PCH Trace Hub Enable Mode

Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' if Trace Hub is used by target debugger software. Note: If 'Host Debugger' is selected, Platform Debug Consent has to be ENABLED because DCI is one of the primary trace data output paths.

PCH TH Mem Buffer Size 0

Select size of memory region 0 buffer. Choose None/OS if OS-supported memory or trace forwarding is desired Note : Limit of total buffer size (PCH + CPU) is 512MB when iTBT disabled, 256MB when iTBT enabled

PCH TH Mem Buffer Size 1

Select size of memory region 1 buffer. Choose None/OS if OS-supported memory or trace forwarding is desired Note : Limit of total buffer size (PCH + CPU) is 512MB when iTBT disabled, 256MB when iTBT enabled

CPU Trace Hub Enable Mode

CPU TH Mem Buffer Size 0

CPU TH Mem Buffer Size 1

CPU Run Control

Enable/Disable CPU Run Control Support; No Change : Comply with HW value

CPU Run Control Lock

Enable/Disable CPU Run Control Lock

USB Overcurrent Override for DbC

This option overrides USB Over Current enablement state that USB OC will be disabled after enabling this option. Enable when DbC is used to avoid signaling conflicts.

Processor trace memory allocation

Disable or Select Processor trace memory region Size: from 4KB ~ 128MB

Processor trace

Enable/Disable processor trace feature from CPU MSR. Enabling this feature will immediately start trace collection.

Processor Trace OutPut Scheme

Select Single Range Output scheme or ToPA table Output scheme

JTAG C10 Power Gate

When Enabled, JTAG is power gated in C10 state. When Disabled, keeps the JTAG power up during C10 and deeper power states for debug purpose.

Three Strike Counter

Enable/Disable Three Strike Counter

CrashLog Feature

The feature helps collecting crash data from PMC SSRAM

CrashLog On All Reset

Option to invoke CrashLog collection on all reset

CrashLog Clear Enable

Option to invoke CrashLog clear

PMC Debug Message Enable

When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix

Delayed Authentication Mode

Enable/Disable Delayed Authentication Mode

PCI Settings

PCI Bus Driver Version 00.00

PCI ROM Priority

In case of multiple Option ROMs (Legacy and EFI Compatible), specifies what PCI Option rom to launch.

External DMA Allowed On Boot

External DMA Allowed On Boot for devices such as 1394, PCMCIA, & CardBus

Install Ext OpRom Before BIOS Setup

Install Ext OpRom for Storage or Other device before BIOS Setup, That we can get the Ext PCIE Card OpRom Setup Menu and have chance to enter into it

PCI Latency Timer

Value to be programmed into PCI Latency Timer Register.

ACPI Settings

ACPI Version N/A

Enable ACPI Auto Configuration Enabled

Enables or Disables BIOS ACPI Auto Configuration.

Enable Hibernation Enabled

Enables or Disables System ability to Hibernate (OS/S4 Sleep State). This option may not be effective with some OSs.

PTID Support Enabled

PTID Support will be loaded if enabled.

PECI Access Method

PECI Access Method is Direct I/O or ACPI

ACPI S3 Support

Enable ACPI S3 support

Native PCIE Enable

Bit - PCIe Native * control 0 - ~ Hot Plug 1 - SHPC Native Hot Plug control 2 - ~ Power Management Events 3 - PCIe Advanced Error Reporting control 4 - PCIe Capability Structure control 5 - Latency Tolerance Reporting control

Native ASPM

Enabled - OS Controlled ASPM, Disabled - BIOS Controlled ASPM

BDAT ACPI Table Support

Enables support for the BDAT ACPI table.

ACPI Debug

Open a memory buffer for storing debug strings. Reenter SETUP after enabling to see the buffer address. Use method ADBG to write strings to buffer.

Acpi Memory Buffer Address N/A

Print to Serial Port

Print copy of ACPI debug logs to serial port

Low Power S0 Idle Capability

This variable determines if we enable ACPI Lower Power S0 Idle Capability (Mutually exclusive with Smart connect). While this is enabled, it also disable 8254 timer for SLP_S0 support.

PUIS Enable

Enable/Disable Power-Up In Standby (PUIS) feature set allows devices to be powered-up into the Standby power management state to minimize inrush current at power-up and to allow the host to sequence the spin-up of devices.

EC Notification

Sends EC notification of Low Power S0 Idle State

EC CS Debug Light

When EC enters Low Power S0 Idle State, the CAPS LOCK light will be turned on

EC Low Power Mode

This option controls whether EC will go to Low power mode during Low Power S0 Idle State

Sensor Standby

Enable/Disable Sensor standby mode

CS PL1 Limit

Limit PL1 (Power Limit 1) while in Connected Standby

CS PL1 Value

PL1 value is in milliwatts with 125 step value

PEP Constraints Configuration

LPIT Residency Counter

Select Residency Counter

Intel Ready Mode Technology

Enable/Disable Ready Mode support based on Windows Away-mode. Only on DT/AIO.

SSDT table from file

PCI Delay Optimization

Experimental ACPI additions for FW latency optimizations

MSI enabled

When disabled, MSI support is disabled in FADT

PEP Constraints Configuration

PEP CPU

Add CPU in PEP mitigation list

PEP Graphics

Add Gfx in PEP mitigation list

PEP GNA

Add GNA in PEP mitigation list

PEP SATA

Add Storage device in PEP mitigation list

PEP enumerated SATA ports

Add enumerated SATA ports in PEP Constraint list

PEP PCIe Storage

Add PCIe Storage devices in PEP mitigation list

PEP PCIe LAN

Add PCIe LAN device in PEP mitigation list

PEP PCIe WLAN

PEP PCIe GFX

PEP PCIe Other

PEP UART

Add UART in PEP mitigation list

PEP I2C0

Adds I2C in PEP mitigation list

PEP I2C1

Adds I2C in PEP mitigation list

PEP I2C2

Adds I2C in PEP mitigation list

PEP I2C3

Adds I2C in PEP mitigation list

PEP I2C4

Adds I2C in PEP mitigation list

PEP I2C5

Adds I2C in PEP mitigation list

PEP SPI

Add SPI in PEP mitigation list

PEP XHCI

Add XHCI in PEP mitigation list

PEP Audio

Add Audio in PEP mitigation list

PEP CSME

Add CSME in PEP mitigation list

PEP HECI3

Add HECI3 in PEP mitigation list

PEP LAN(GBE)

Add LAN(GBE) in PEP mitigation list

PEP THC0

Add THC in PEP mitigation list. Applies only if THCx has assigned port

PEP THC1

Add THC in PEP mitigation list. Applies only if THCx has assigned port

PEP TCSS

Add TCSS IPs in PEP mitigation list

PEP VMD

Add VMD in PEP mitigation list

CPU Configuration

Type N/A

ID N/A

Speed N/A

L1 Data Cache N/A

L1 Instruction Cache N/A

L2 Cache N/A

L3 Cache N/A

L4 Cache N/A

VMX N/A

SMX/TXT N/A

C6DRAM

Enable/Disable moving of DRAM contents to PRM memory when CPU is in C6 state

CPU Flex Ratio Override

Enable/Disable CPU Flex Ratio Programming

CPU Flex Ratio Settings

This value must be between Max Efficiency Ratio (LFM) and Maximum non-turbo ratio set by Hardware (HFM).

Hardware Prefetcher

To turn on/off the MLC streamer prefetcher.

Adjacent Cache Line Prefetch

To turn on/off prefetching of adjacent cache lines.

Intel (VMX) Virtualization Technology

When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology.

PECI

Enable/Disable PECI

AVX

Enable/Disable the AVX 2/3 Instructions. This is applicable for Big Core only

AVX3

Enable/Disable the AVX 3 Instructions. This is applicable for Big Core only

Active Processor Cores

Number of cores to enable in each processor package.

Hyper-Threading

Enable or Disable Hyper-Threading Technology.

BIST

Enable/Disable BIST (Built-In Self Test) on reset

AP threads Idle Manner

AP threads Idle Manner for waiting signal to run

AES

Enable/Disable AES (Advanced Encryption Standard)

MachineCheck

Enable/Disable Machine Check

MonitorMWait

Enable/Disable MonitorMWait

Intel Trusted Execution Technology

Enables utilization of additional hardware capabilities provided by Intel (R) Trusted Execution Technology. Changes require a full power cycle to take effect.

Alias Check Request

Enables Txt Alias Checking capability Changes require full Txt capability before it will take effect. It is a one time only change, next reboot will be reset.

DPR Memory Size (MB)

Reserve DPR memory size (0-255) MB

Reset AUX Content

Reset TPM Aux content. Txt may not functional after AUX content gets reset.

CPU SMM Enhancement

FCLK Frequency for Early Power On

FCLK frequency can take values of 400MHz, 800MHz and 1GHz (1GHz not supported for ULT/ULX SKUs)

BIOS Guard

Enable Tools Interface

Configure Tools Interface. Options are: DISABLE - Disable Tools Interface; ENABLE - Enable Tools Interface.

CPU SMM Enhancement

SMM MSR Save State Enable

Enable/Disable support for MSR Save State

SMM Use Delay Indication

Enable/Disable usage of SMM_DELAYED MSR for MP sync in SMI

SMM Use Block Indication

Enable/Disable usage of SMM_BLOCKED MSR for MP sync in SMI

SMM Use SMM en-US Indication

Enable/Disable usage of SMM_ENABLE MSR for MP sync in SMI

Power & Performance

CPU - Power Management Control

GT - Power Management Control

Intel(R) Speed Shift Technology Interrupt Control

Enable/Disable Intel(R) Speed Shift Technology Interrupts

CPU - Power Management Control

Core 0 Fused Max Core Ratio N/A

Core 1 Fused Max Core Ratio N/A

Core 2 Fused Max Core Ratio N/A

Core 3 Fused Max Core Ratio N/A

Core 4 Fused Max Core Ratio N/A

Core 5 Fused Max Core Ratio N/A

Core 6 Fused Max Core Ratio N/A

Core 7 Fused Max Core Ratio N/A

Core 8 Fused Max Core Ratio N/A

Core 9 Fused Max Core Ratio N/A

Boot performance mode

Select the performance state that the BIOS will set starting from reset vector.

Intel(R) SpeedStep(tm)

Allows more than two frequency ranges to be supported.

Race To Halt (RTH)

Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency in order to enter pkg C-State faster to reduce overall power. (RTH is controlled through MSR 1FC bit 20)

Intel(R) Speed Shift Technology

Enable/Disable Intel(R) Speed Shift Technology support. Enabling will expose the CPPC v2 interface to allow for hardware controlled P-states.

Intel(R) Turbo Boost Max Technology 3.0

Enable/Disable Intel(R) Turbo Boost Max Technology 3.0 support. Disabling will report the maximum ratio of the slowest core in _CPC object.

Per Core P State OS control mode

Enable/Disable Per Core P state OS control mode. Disabling will set Bit 31 = 1 command 0x06. When set, the highest core request is used for all other core requests.

HwP Autonomous Per Core P State

Disable Autonomous PCPS (Bit 30 = 1, command 0x11) Autonomous will request the same value for all cores all the time. Enable PCPS (default Bit 30 = 0, command 0x11)

HwP Autonomous EPP Grouping

Enable EPP grouping (default Bit 29 =0, command 0x11) Autonomous will request the same values for all cores with same EPP. Disable EPP grouping (Bit 29 =1 , command 0x11) autonomous will not necessarily request same values for all cores with same EPP.

EPB override over PECI

Enable/Disable EPB override over PECI. Enable by sending pcode command 0x2b , subcommand 0x3 to 1. This will allow OOB EPB PECI override control

HwP Fast MSR Support

Enable/Disable HwP Fast MSR Support for IA32_HWP_REQUEST MSR.

HDC Control

This option allows HDC configuration. Disabled: Disable HDC Enabled: Can be enabled by OS if OS native support is available.

Turbo Mode

Enable/Disable processor Turbo Mode (requires EMTTM enabled too). AUTO means enabled.

View/Configure Turbo Options

Config TDP Configurations

CPU VR Settings

Platform PL1 Enable

Enable/Disable Platform Power Limit 1 programming. If this option is enabled, it activates the PL1 value to be used by the processor to limit the average power of given time window.

Platform PL1 Power

Platform Power Limit 1 Power in Milli Watts. BIOS will round to the nearest 1/8W when programming. Any value can be programmed between Max and Min Power Limits (specified by PACKAGE_POWER_SKU_MSR). For 12.50W, enter 12500. This setting will act as the new PL1 value for the Package RAPL algorithm.

Platform PL1 Time Window

Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default values. Indicates the time window over which Platform TDP value should be maintained.

Platform PL2 Enable

Enable/Disable Platform Power Limit 2 programming. If this option is disabled, BIOS will program the default values for Platform Power Limit 2.

Platform PL2 Power

Platform Power Limit 2 Power in Milli Watts. BIOS will round to the nearest 1/8W when programming. Any value can be programmed between Max and Min Power Limits (specified by PACKAGE_POWER_SKU_MSR). For 12.50W, enter 12500. This setting will act as the new PL2 value for the Package RAPL algorithm.

Power Limit 4 Override

Enable/Disable Power Limit 4 override. If this option is disabled, BIOS will leave the default values for Power Limit 4.

Power Limit 4

Power Limit 4 in Milli Watts. BIOS will round to the nearest 1/8W when programming. For 12.50W, enter 12500. If the value is 0, BIOS leaves default value

Power Limit 4 Lock

Power Limit 4 MSR 601h Lock. When enabled PL4 configurations are locked during OS. When disabled PL4 configuration can be changed during OS.

C states

Enable/Disable CPU Power Management. Allows CPU to go to C states when it's not 100% utilized.

Enhanced C-states

Enable/Disable C1E. When enabled, CPU will switch to minimum speed when all cores enter C-State.

C-State Auto Demotion

Configure C-State Auto Demotion

C-State Un-demotion

Configure C-State Un-demotion

Package C-State Demotion

Package C-State Un-demotion

CState Pre-Wake

Disable - Sets bit 30 of POWER_CTL MSR(0x1FC) to 1 to disable the Cstate Pre-Wake

IO MWAIT Redirection

When set, will map IO_read instructions sent to IO registers PMG_IO_BASE_ADDRBASE+offset to MWAIT(offset)

Package C State Limit

Maximum Package C State Limit Setting. Cpu Default: Leaves to Factory default value.Auto: Initializes to deepest available Package C State Limit.

C3 Latency Control(MSR 0x60A)

Time Unit

Unit of measurement for IRTL value - bits [12:10]

Latency

Interrupt Response Time Limit value- bits [9:0], Enter 0-1023

C6/C7 Short Latency Control(MSR 0x60B)

Time Unit

Unit of measurement for IRTL value - bits [12:10]

Latency

Interrupt Response Time Limit value- bits [9:0], Enter 0-1023

C6/C7 Long Latency Control(MSR 0x60C)

Time Unit

Unit of measurement for IRTL value - bits [12:10]

Latency

Interrupt Response Time Limit value- bits [9:0], Enter 0-1023

C8 Latency Control(MSR 0x633)

Time Unit

Unit of measurement for IRTL value - bits [12:10]

Latency

Interrupt Response Time Limit value- bits [9:0], Enter 0-1023

C9 Latency Control(MSR 0x634)

Time Unit

Unit of measurement for IRTL value - bits [12:10]

Latency

Interrupt Response Time Limit value- bits [9:0], Enter 0-1023

C10 Latency Control(MSR 0x635)

Time Unit

Unit of measurement for IRTL value - bits [12:10]

Latency

Interrupt Response Time Limit value- bits [9:0], Enter 0-1023

Thermal Monitor

Enable/Disable Thermal Monitor

Interrupt Redirection Mode Selection

Interrupt Redirection Mode Select for Logical Interrupts

Timed MWAIT

Enable/Disable Timed MWAIT Support

Custom P-state Table

EC Turbo Control Mode

Enable/Disable EC Turbo Control mode

AC Brick Capacity

Specify the AC Brick capacity

EC Polling Period

Count 1 to 255 for a range of 10ms to 2.55 seconds (1 count = 10ms)

EC Guard Band Value

Count 1 to 20 for a range of 1 watt to 20 watts

EC Algorithm Selection

Count 1 to 10 for Algorithm Selection

Energy Performance Gain

Enable/disable Energy Performance Gain.

EPG DIMM Idd3N

Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on a per DIMM basis.

EPG DIMM Idd3P

Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated on a per DIMM basis.

Power Limit 3 Settings

CPU Lock Configuration

Dual Tau Boost

Enable Dual Tau Boost feature. This is only applicable for Desktop 35W/65W/125W sku. When DPTF is enabled this feature is ignored.

Custom P-state Table

Number of P states

Sets the number of custom P-states. At least 2 states must be present.

Max P-State Ratio

Maximum P-state ratio to use in the custom P-state table.

P-State Ratio

P-state ratio for the given state in the custom P-state table.

P-State Ratio

P-state ratio for the given state in the custom P-state table.

P-State Ratio

P-state ratio for the given state in the custom P-state table.

P-State Ratio

P-state ratio for the given state in the custom P-state table.

P-State Ratio

P-state ratio for the given state in the custom P-state table.

P-State Ratio

P-state ratio for the given state in the custom P-state table.

P-State Ratio

P-state ratio for the given state in the custom P-state table.

P-State Ratio

P-state ratio for the given state in the custom P-state table.

P-State Ratio

P-state ratio for the given state in the custom P-state table.

P-State Ratio

P-state ratio for the given state in the custom P-state table.

P-State Ratio

P-state ratio for the given state in the custom P-state table.

P-State Ratio

P-state ratio for the given state in the custom P-state table.

P-State Ratio

P-state ratio for the given state in the custom P-state table.

P-State Ratio

P-state ratio for the given state in the custom P-state table.

P-State Ratio

P-state ratio for the given state in the custom P-state table.

P-State Ratio

P-state ratio for the given state in the custom P-state table.

P-State Ratio

P-state ratio for the given state in the custom P-state table.

P-State Ratio

P-state ratio for the given state in the custom P-state table.

P-State Ratio

P-state ratio for the given state in the custom P-state table.

P-State Ratio

P-state ratio for the given state in the custom P-state table.

P-State Ratio

P-state ratio for the given state in the custom P-state table.

P-State Ratio

P-state ratio for the given state in the custom P-state table.

P-State Ratio

P-state ratio for the given state in the custom P-state table.

P-State Ratio

P-state ratio for the given state in the custom P-state table.

P-State Ratio

P-state ratio for the given state in the custom P-state table.

P-State Ratio

P-state ratio for the given state in the custom P-state table.

P-State Ratio

P-state ratio for the given state in the custom P-state table.

P-State Ratio

P-state ratio for the given state in the custom P-state table.

P-State Ratio

P-state ratio for the given state in the custom P-state table.

P-State Ratio

P-state ratio for the given state in the custom P-state table.

P-State Ratio

P-state ratio for the given state in the custom P-state table.

P-State Ratio

P-state ratio for the given state in the custom P-state table.

P-State Ratio

P-state ratio for the given state in the custom P-state table.

P-State Ratio

P-state ratio for the given state in the custom P-state table.

P-State Ratio

P-state ratio for the given state in the custom P-state table.

P-State Ratio

P-state ratio for the given state in the custom P-state table.

P-State Ratio

P-state ratio for the given state in the custom P-state table.

P-State Ratio

P-state ratio for the given state in the custom P-state table.

P-State Ratio

P-state ratio for the given state in the custom P-state table.

Max 16 custom P-state Table

Max P-State Ratio (Max 16 table)

P-state ratio for the given state in the Max 16 P-state table. Used if OS only supports 16 P-states

P-State Ratio (Max 16 table)

P-state ratio for the given state in the Max 16 P-state table. Used if OS only supports 16 P-states

P-State Ratio (Max 16 table)

P-state ratio for the given state in the Max 16 P-state table. Used if OS only supports 16 P-states

P-State Ratio (Max 16 table)

P-state ratio for the given state in the Max 16 P-state table. Used if OS only supports 16 P-states

P-State Ratio (Max 16 table)

P-state ratio for the given state in the Max 16 P-state table. Used if OS only supports 16 P-states

P-State Ratio (Max 16 table)

P-state ratio for the given state in the Max 16 P-state table. Used if OS only supports 16 P-states

P-State Ratio (Max 16 table)

P-state ratio for the given state in the Max 16 P-state table. Used if OS only supports 16 P-states

P-State Ratio (Max 16 table)

P-state ratio for the given state in the Max 16 P-state table. Used if OS only supports 16 P-states

P-State Ratio (Max 16 table)

P-state ratio for the given state in the Max 16 P-state table. Used if OS only supports 16 P-states

P-State Ratio (Max 16 table)

P-state ratio for the given state in the Max 16 P-state table. Used if OS only supports 16 P-states

P-State Ratio (Max 16 table)

P-state ratio for the given state in the Max 16 P-state table. Used if OS only supports 16 P-states

P-State Ratio (Max 16 table)

P-state ratio for the given state in the Max 16 P-state table. Used if OS only supports 16 P-states

P-State Ratio (Max 16 table)

P-state ratio for the given state in the Max 16 P-state table. Used if OS only supports 16 P-states

P-State Ratio (Max 16 table)

P-state ratio for the given state in the Max 16 P-state table. Used if OS only supports 16 P-states

P-State Ratio (Max 16 table)

P-state ratio for the given state in the Max 16 P-state table. Used if OS only supports 16 P-states

Min P-State Ratio (Max 16 table)

P-state ratio for the given state in the Max 16 P-state table. Used if OS only supports 16 P-states

Current Turbo Ratio Limit Settings

Turbo Ratio Limit Core0 (TRLC)

Turbo Ratio Limit Core1 (TRLC)

Turbo Ratio Limit Core2 (TRLC)

Turbo Ratio Limit Core3 (TRLC)

Turbo Ratio Limit Core4 (TRLC)

Turbo Ratio Limit Core5 (TRLC)

Turbo Ratio Limit Core6 (TRLC)

Turbo Ratio Limit Core7 (TRLC)

Turbo Ratio Limit Ratio0 (TRLR)

Turbo Ratio Limit Ratio1 (TRLR)

Turbo Ratio Limit Ratio2 (TRLR)

Turbo Ratio Limit Ratio3 (TRLR)

Turbo Ratio Limit Ratio4 (TRLR)

Turbo Ratio Limit Ratio5 (TRLR)

Turbo Ratio Limit Ratio6 (TRLR)

Turbo Ratio Limit Ratio7 (TRLR)

Turbo Ratio Limit Core0

Turbo Ratio Limit Core0 defines the core range, the turbo ratio is defined in Turbo Ratio Limit Ratio0. If value is zero, this entry is ignored.

Turbo Ratio Limit Core1

Turbo Ratio Limit Core1 defines the core range, the turbo ratio is defined in Turbo Ratio Limit Ratio1. If value is zero, this entry is ignored.

Turbo Ratio Limit Core2

Turbo Ratio Limit Core2 defines the core range, the turbo ratio is defined in Turbo Ratio Limit Ratio2. If value is zero, this entry is ignored.

Turbo Ratio Limit Core3

Turbo Ratio Limit Core3 defines the core range, the turbo ratio is defined in Turbo Ratio Limit Ratio3. If value is zero, this entry is ignored.

Turbo Ratio Limit Core4

Turbo Ratio Limit Core4 defines the core range, the turbo ratio is defined in Turbo Ratio Limit Ratio4. If value is zero, this entry is ignored.

Turbo Ratio Limit Core5

Turbo Ratio Limit Core5 defines the core range, the turbo ratio is defined in Turbo Ratio Limit Ratio5. If value is zero, this entry is ignored.

Turbo Ratio Limit Core6

Turbo Ratio Limit Core6 defines the core range, the turbo ratio is defined in Turbo Ratio Limit Ratio6. If value is zero, this entry is ignored.

Turbo Ratio Limit Core7

Turbo Ratio Limit Core7 defines the core range, the turbo ratio is defined in Turbo Ratio Limit Ratio7. If value is zero, this entry is ignored.

Turbo Ratio Limit Ratio0 (TRLR)

Turbo Ratio Limit Ratio0 (TRLR) with range of Max Non-Turbo Ratio to 120.This Turbo Ratio Limit Ratio0 must be greater than or equal all other ratio values. If this value is invalid, thn set all other active cores to minimum. Otherwise, align the Ratio Limit to 0. Please check each active cores

Turbo Ratio Limit Ratio1 (TRLR)

Turbo Ratio Limit Ratio1 (TRLR) with range of Max Non-Turbo Ratio to 120.This Turbo Ratio Limit Ratio1 must be <= to Turbo Ratio Limit Ratio0.

Turbo Ratio Limit Ratio2 (TRLR)

Turbo Ratio Limit Ratio2 (TRLR) with range of Max Non-Turbo Ratio to 120.This Turbo Ratio Limit Ratio2 must be <= to Turbo Ratio Limit Ratio1.

Turbo Ratio Limit Ratio3 (TRLR)

Turbo Ratio Limit Ratio3 (TRLR) with range of Max Non-Turbo Ratio to 120.This Turbo Ratio Limit Ratio3 must be <= to Turbo Ratio Limit Ratio2.

Turbo Ratio Limit Ratio4 (TRLR)

Turbo Ratio Limit Ratio4 (TRLR) with range of Max Non-Turbo Ratio to 120.This Turbo Ratio Limit Ratio4 must be <= to Turbo Ratio Limit Ratio3.

Turbo Ratio Limit Ratio5 (TRLR)

Turbo Ratio Limit Ratio5 (TRLR) with range of Max Non-Turbo Ratio to 120.This Turbo Ratio Limit Ratio5 must be <= to Turbo Ratio Limit Ratio4.

Turbo Ratio Limit Ratio6 (TRLR)

Turbo Ratio Limit Ratio6 (TRLR) with range of Max Non-Turbo Ratio to 120.This Turbo Ratio Limit Ratio6 must be <= to Turbo Ratio Limit Ratio5.

Turbo Ratio Limit Ratio7 (TRLR)

Turbo Ratio Limit Ratio7 (TRLR) with range of Max Non-Turbo Ratio to 120.This Turbo Ratio Limit Ratio7 must be <= to Turbo Ratio Limit Ratio6.

Current Turbo Settings

Max Turbo Power Limit

Min Turbo Power Limit

Package TDP Limit

Power Limit 1

Power Limit 2

Turbo Ratio Limit Options

Energy Efficient P-state

Enable/Disable Energy Efficient P-state feature. When set to 0, will disable access to ENERGY_PERFORMANCE_BIAS MSR and CPUID Function 6 ECX[3] will read 0 indicating no support for Energy Efficient policy setting. When set to 1 will enable access to ENERGY_PERFORMANCE_BIAS MSR 1B0h and CPUID Function 6 ECX[3] will read 1 indicating Energy Efficient policy setting is supported.

Package Power Limit MSR Lock

Enable/Disable locking of Package Power Limit settings. When enabled, PACKAGE_POWER_LIMIT MSR will be locked and a reset will be required to unlock the register.

Power Limit 1 Override

Enable/Disable Power Limit 1 override. If this option is disabled, BIOS will program the default values for Power Limit 1 and Power Limit 1 Time Window.

Power Limit 1

Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming. 0 = no custom override. For 12.50W, enter 12500. Overclocking SKU: Value must be between Max and Min Power Limits (specified by PACKAGE_POWER_SKU_MSR). Other SKUs: This value must be between Min Power Limit and TDP Limit. If value is 0, BIOS will program TDP value.

Power Limit 1 Time Window

Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.

Power Limit 2 Override

Enable/Disable Power Limit 2 override. If this option is disabled, BIOS will program the default values for Power Limit 2.

Power Limit 2

Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming. If the value is 0, BIOS will program this value as 1.25*TDP. For 12.50W, enter 12500. Processor applies control policies such that the package power does not exceed this limit.

Energy Efficient Turbo

Enable/Disable Energy Efficient Turbo Feature. This feature will opportunistically lower the turbo frequency to increase efficiency. Recommended only to disable in overclocking situations where turbo frequency must remain constant. Otherwise, leave enabled.

CPU VR Settings

VR Power Delivery Design

Specifies the RKL-S board design used for the VR settings override values. By default, BIOS will override the default RKL-S VR settings based on the board design. A value of AUTO(0) will use the board ID to determine the board design. Any other value will override the board id logic to provide a custom VR Power Delivery Design value. This is intended primarily for validation.

PSYS Slope

PSYS Slope defined in 1/100 increments. Range is 0-200. For a 1.25 slope, enter 125. 0 = AUTO. Uses BIOS VR mailbox command 0x9."

PSYS Offset

PSYS Offset defined in 1/1000 increments. Range is 0-63999. For an offset of 25.348, enter 25348. PSYS Uses BIOS VR mailbox command 0x4.

PSYS Prefix

Sets the offset value as positive or negative.

PSYS PMax Power

PSYS PMax power, defined in 1/8 Watt increments. Range 0-8192. For a PMax of 125W, enter 1000. 0 = AUTO. Uses BIOS VR mailbox command 0xB.

Min Voltage Override

Min Voltage Override. Enable to override minimum voltage for runtime and for C8.

Min Voltage Runtime

Min Voltage for Runtime. Range is 0 - 1999mV in 1/128 volt increments. Input is in mVolts.

Min Voltage C8

Min Voltage for Package C8. Range is 0 - 1999mV in 1/128 volt increments. Input is in mVolts.

Acoustic Noise Settings

System Agent VR Settings

Core/IA VR Settings

GT VR Settings

RFI Settings

Acoustic Noise Settings

Acoustic Noise Mitigation

Enabling this option will help mitigate acoustic noise on certain SKUs when the CPU is in deeper C state

Pre Wake Time

Set the maximum Pre Wake randomization time in micro ticks. Range is 0-255. This is for acoustic noise mitigation Dynamic Perodicity Alteration (DPA) tuning.

Ramp Up Time

Set the maximum Ramp Up randomization time in micro ticks. Range is 0-255. This is for acoustic noise mitigation Dynamic Perodicity Alteration (DPA) tuning.

Ramp Down Time

Set the maximum Ramp Down randomization time in micro ticks. Range is 0-255. This is for acoustic noise mitigation Dynamic Perodicity Alteration (DPA) tuning.

IA VR Domain

Disable Fast PKG C State Ramp for IA Domain

This option needs to be configured to reduce acoustic noise during deeper C states. False: Don't disable Fast ramp during deeper C states; True: Disable Fast ramp during deeper C state

Slow Slew Rate for IA Domain

Set VR IA Slow Slew Rate for Deep Package C State ramp time; Slow slew rate equals to Fast divided by number, the number is 2, 4, 8, 16 to slow down the slew rate to help minimize acoustic noise

GT VR Domain

Disable Fast PKG C State Ramp for GT Domain

This option needs to be configured to reduce acoustic noise during deeper C states. False: Don't disable Fast ramp during deeper C states; True: Disable Fast ramp during deeper C state

Slow Slew Rate for GT Domain

Set VR GT Slow Slew Rate for Deep Package C State ramp time; Slow slew rate equals to Fast divided by number, the number is 2, 4, 8, 16 to slow down the slew rate to help minimize acoustic noise

SA VR Domain

Disable Fast PKG C State Ramp for SA Domain

This option needs to be configured to reduce acoustic noise during deeper C states. False: Don't disable Fast ramp during deeper C states; True: Disable Fast ramp during deeper C state

Slow Slew Rate for SA Domain

Set VR SA Slow Slew Rate for Deep Package C State ramp time; Slow slew rate equals to Fast devided by number, the number is 2, 4, 8 to slow down the slew rate to help minimize acoustic noise; divide by 16 is disabled

System Agent VR Domain

VR Config Enable

Current AC Loadline

Current DC Loadline

Current Psi1 Threshold

Current Psi2 Threshold

Current Psi3 Threshold

Current Imon Slope

Current Imon Offset

Current VR Current Limit

Current VR Voltage Limit

Current Tdc Current Limit

AC Loadline

AC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. Uses BIOS mailbox command 0x2.

DC Loadline

DC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. Uses BIOS mailbox command 0x2.

PS Current Threshold1

PS Current Threshold1, defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = AUTO. Uses BIOS VR mailbox command 0x3.

PS Current Threshold2

PS Current Threshold2, defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = AUTO. Uses BIOS VR mailbox command 0x3.

PS Current Threshold3

PS Current Threshold3, defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = AUTO. Uses BIOS VR mailbox command 0x3.

PS3 Enable

PS3 Enable/Disable. 0 - Disabled, 1 - Enabled.Uses BIOS VR mailbox command 0x3.

PS4 Enable

PS4 Enable/Disable. 0 - Disabled, 1 - Enabled. Uses BIOS VR mailbox command 0x3

IMON Slope

IMON Slope defined in 1/100 increments. Range is 0-200. For a 1.25 slope, enter 125. 0 = AUTO. Uses BIOS VR mailbox command 0x4.

IMON Offset

IMON Offset defined in 1/1000 increments. Range is 0-63999. For an offset of 25.348, enter 25348. IMON Uses BIOS VR mailbox command 0x4.

IMON Prefix

Sets the offset value as positive or negative.

VR Current Limit

Voltage Regulator Current Limit (Icc Max). This value represents the Maximum instantaneous current allowed at any given time. The value is represented in 1/4 A increments. A value of 400 = 100A. 0 means AUTO. Uses BIOS VR mailbox command 0x6.

VR Voltage Limit

VR Voltage Limit, defined in mV. Range is 0-7999mV. For a Voltage Limit of 1.25V, enter 1250. 0 = AUTO. Uses BIOS VR mailbox command 0x6

TDC Enable

TDC Enable. 0- Disable, 1 - Enable

TDC Current Limit

TDC Current Limit, defined in 1/8A increments. Range 0-32767. For a TDC Current Limit of 125A, enter 1000. 0 = 0 Amps. Uses BIOS VR mailbox command 0x1A.

TDC Time Window

TDC Time Window, value in milliseconds. 1ms is default. Range from 1ms to 10ms, except for 9ms. 9ms has no valid encoding in the MSR definition.

TDC Lock

Core/IA VR Domain

VR Config Enable

Current AC Loadline

Current DC Loadline

Current Psi1 Threshold

Current Psi2 Threshold

Current Psi3 Threshold

Current Imon Slope

Current Imon Offset

Current VR Current Limit

Current VR Voltage Limit

Current Tdc Current Limit

AC Loadline

AC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. Uses BIOS mailbox command 0x2.

DC Loadline

DC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. Uses BIOS mailbox command 0x2.

PS Current Threshold1

PS Current Threshold1, defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = AUTO. Uses BIOS VR mailbox command 0x3.

PS Current Threshold2

PS Current Threshold2, defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = AUTO. Uses BIOS VR mailbox command 0x3.

PS Current Threshold3

PS Current Threshold3, defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = AUTO. Uses BIOS VR mailbox command 0x3.

PS3 Enable

PS3 Enable/Disable. 0 - Disabled, 1 - Enabled.Uses BIOS VR mailbox command 0x3.

PS4 Enable

PS4 Enable/Disable. 0 - Disabled, 1 - Enabled. Uses BIOS VR mailbox command 0x3

IMON Slope

IMON Slope defined in 1/100 increments. Range is 0-200. For a 1.25 slope, enter 125. 0 = AUTO. Uses BIOS VR mailbox command 0x4.

IMON Offset

IMON Offset defined in 1/1000 increments. Range is 0-63999. For an offset of 25.348, enter 25348. IMON Uses BIOS VR mailbox command 0x4.

IMON Prefix

Sets the offset value as positive or negative.

VR Current Limit

VR Voltage Limit

VR Voltage Limit, defined in mV. Range is 0-7999mV. For a Voltage Limit of 1.25V, enter 1250. 0 = AUTO. Uses BIOS VR mailbox command 0x6

TDC Enable

TDC Enable. 0- Disable, 1 - Enable

TDC Current Limit

TDC Current Limit, defined in 1/8A increments. Range 0-32767. For a TDC Current Limit of 125A, enter 1000. 0 = 0 Amps. Uses BIOS VR mailbox command 0x1A.

TDC Time Window

TDC Time Window, value in milliseconds. 1ms is default. Range from 1ms to 10ms, except for 9ms. 9ms has no valid encoding in the MSR definition.

TDC Lock

IRMS

Enable/Disable IRMS - Current root mean square

GT Domain

VR Config Enable

Current AC Loadline

Current DC Loadline

Current Psi1 Threshold

Current Psi2 Threshold

Current Psi3 Threshold

Current Imon Slope

Current Imon Offset

Current VR Current Limit

Current VR Voltage Limit

Current Tdc Current Limit

AC Loadline

AC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. Uses BIOS mailbox command 0x2.

DC Loadline

DC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. Uses BIOS mailbox command 0x2.

PS Current Threshold1

PS Current Threshold1, defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = AUTO. Uses BIOS VR mailbox command 0x3.

PS Current Threshold2

PS Current Threshold2, defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = AUTO. Uses BIOS VR mailbox command 0x3.

PS Current Threshold3

PS Current Threshold3, defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = AUTO. Uses BIOS VR mailbox command 0x3.

PS3 Enable

PS3 Enable/Disable. 0 - Disabled, 1 - Enabled.Uses BIOS VR mailbox command 0x3.

PS4 Enable

PS4 Enable/Disable. 0 - Disabled, 1 - Enabled. Uses BIOS VR mailbox command 0x3

IMON Slope

IMON Slope defined in 1/100 increments. Range is 0-200. For a 1.25 slope, enter 125. 0 = AUTO. Uses BIOS VR mailbox command 0x4.

IMON Offset

IMON Offset defined in 1/1000 increments. Range is 0-63999. For an offset of 25.348, enter 25348. IMON Uses BIOS VR mailbox command 0x4.

IMON Prefix

Sets the offset value as positive or negative.

VR Current Limit

VR Voltage Limit

VR Voltage Limit, defined in mV. Range is 0-7999mV. For a Voltage Limit of 1.25V, enter 1250. 0 = AUTO. Uses BIOS VR mailbox command 0x6

TDC Enable

TDC Enable. 0- Disable, 1 - Enable

TDC Current Limit

TDC Current Limit, defined in 1/8A increments. Range 0-32767. For a TDC Current Limit of 125A, enter 1000. 0 = 0 Amps. Uses BIOS VR mailbox command 0x1A.

TDC Time Window

TDC Time Window, value in milliseconds. 1ms is default. Range from 1ms to 10ms, except for 9ms. 9ms has no valid encoding in the MSR definition.

TDC Lock

RFI Domain

RFI Current Frequency

RFI Frequency

Set desired RFI frequency, in increments of 100KHz. (For a frequency of 100.6MHz, enter 1006.)

FIVR Spread Spectrum

Enable or Disable the FIVR Spread Spectrum

RFI Spread Spectrum

Set the Spread Spectrum

Power Limit 3 Override

Enable/DisablePower Limit 3 override. If this option is disabled, BIOS will leave the hardware default values for Power Limit 3 and Power Limit 3 Time Window.

Power Limit 3

Power Limit 3 in Milli Watts. BIOS will round to the nearest 1/8W when programming. For 12.50W, enter 12500. XE SKU: Any value can be programmed. Overclocking SKU: Value must be between Max and Min Power Limits (specified by PACKAGE_POWER_SKU_MSR). Other SKUs: This value must be between Min Power Limit and TDP Limit. If the value is 0, BIOS leaves the hardware default value

Power Limit 3 Time Window

Power Limit 3 Time Window value in Milli seconds. The value may vary from 3 to 64(max).Indicates the time window over which Power Limit 3 value should be maintained. If the value is 0, BIOS leaves the hardware default value

Power Limit 3 Duty Cycle

Specify the duty cycle in percentage that the CPU is required to maintain over the configured time window. Range is 0-100.

Power Limit 3 Lock

Power Limit 3 MSR 615h Lock. When enabled PL3 configurations are locked during OS. When disabled PL3 configuration can be changed during OS.

Config TDP Configurations

Enable Configurable TDP

Applies TDP initialization settings based on non-cTDP or cTDP. Default is 1: Applies to cTDP; if 0 then applies non-cTDP and BIOS will bypass cTDP initialzation flow

Configurable TDP Boot Mode

Configurable TDP Mode as Nominal/Up/Down/Deactivate TDP selection. Deactivate option will set MSR to Nominal and MMIO to Zero.

Configurable TDP Boot Mode

Configurable TDP Mode as Nominal/Up/Down/Deactivate TDP selection. Deactivate option will set MSR to Nominal and MMIO to Zero.

Configurable TDP Boot Mode

Configurable TDP Mode as Nominal/Up/Down/Deactivate TDP selection. Deactivate option will set MSR to Nominal and MMIO to Zero.

Configurable TDP Lock

Configurable TDP Mode Lock sets the Lock bits on TURBO_ACTIVATION_RATIO and CONFIG_TDP_CONTROL. Note: When CTDP Lock is enabled Custom ConfigTDP Count will be forced to 1 and Custom ConfigTDP Boot Index will be forced to 0.

CTDP BIOS control

Enables CTDP control via runtime ACPI BIOS methods. This "BIOS only" feature does not require EC or driver support.

ConfigTDP Levels

ConfigTDP Turbo Activation Ratio N/A

Power Limit 1 N/A

Power Limit 2 N/A

Custom Settings Nominal

ConfigTDP Nominal N/A

Power Limit 1

Power Limit 2

Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming. 0 = no custom override. For 12.50W, enter 12500. Processor applies control policies such that the package power does not exceed this limit.

Power Limit 1 Time Window

Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.

ConfigTDP Turbo Activation Ratio

Custom value for Turbo Activation Ratio. Needs to be configured with valid values from LFM to Max Turbo. 0 means don't use custom value.

Custom Settings Down

ConfigTDP Level1 N/A

Power Limit 1

Power Limit 2

Power Limit 1 Time Window

Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.

ConfigTDP Turbo Activation Ratio

Custom value for Turbo Activation Ratio. Needs to be configured with valid values from LFM to Max Turbo. 0 means don't use custom value.

Custom Settings Up

ConfigTDP Level2 N/A

Power Limit 1

Power Limit 2

Power Limit 1 Time Window

Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.

ConfigTDP Turbo Activation Ratio

Custom value for Turbo Activation Ratio. Needs to be configured with valid values from LFM to Max Turbo. 0 means don't use custom value.

CFG Lock

Configure MSR 0xE2[15], CFG Lock bit

Overclocking Lock

Enable/Disable Overclocking Lock (BIT 20) in FLEX_RATIO(194) MSR

CNVi present No

CNVi Configuration

CNVi Mode

This option configures Connectivity. [Auto Detection] means that if Discrete solution is discovered it will be enabled by default. Otherwise Integrated solution (CNVi) will be enabled; [Disable Integrated] disables Integrated Solution. NOTE: When CNVi is present, the GPIO pins that are used for radio interface cannot be assigned to the other native function.

BT Core

This is an option intended to Enable/Disable BT Core in CNVi

BT Audio Offload

This is an option to Enable/Disable BT Audio Offload which enables audio input from BT device in HFP format to the audio DSP and enables power efficient audio output to BT device via A2DP format. This feature only support with Intel(R) Wireless-AX 22560

CoExistence Manager

CoEx Manager mitigates radio coexistence issues between Intel WWAN (modem) and Intel WLAN (WiFi/BT). This should be enabled only if both WWAN and WLAN solutions are based on Intel components

Preboot BLE

This will be used to enable Preboot Bluetooth function

BLE Reconnection Delay

Delay prior to connecting BLE host controller. Value between 0-1000ms. Default is 100ms

Discrete Bluetooth Module

SerialIo UART0 needs to be enabled to select BT Module

BT Interrupt Mode

Selects routing of interrupt from BT Module

Advanced settings

Configure ACPI objects for wireless devices

Switched Antenna Diversity Selection

This allows WiFi modules which have only one antenna to use one of the 2 possible antennas with the options: 0 - Antenna1 1 - Antenna2 2 - Diversity 3 - Diversity Antenna1 4 - Diversity Antenna2

Domain Type SPLC 1

09h: Module(M.2); 07h: WiFi/WLAN; 0Fh: WWAN; 10h WiGig; 14h: RFEM

Default Power Limit

Power Limit in milli watts

Default Time Window

Time Window in milli seconds

TRxDelay_A

Antenna A delay possible values: 1-100 in 10ths of nano seconds resolution

TRxCableLength_A

Antenna A cable length possible values: 1-100cm in 1cm resolution

TRxDelay_B

Antenna B delay possible values: 1-100 in 10ths of nano seconds resolution

TRxCableLength_B

Antenna B cable length possible values: 1-100cm in 1cm resolution

WRDD Package 1

Domain Type

09h: Module; 07h: WiFi/WLAN; 0Fh: WWAN; 10h WiGig; 14h: RFEM

Country Identifier

Country identifier as defined in ISO/IEC 3166-1 Alpha 2 code

WRDS Package

WiFi SAR

Enable/Disable WiFi SAR Tx Power Limit; DISABLE - Device ignores WiFi SAR Configuration Table; ENABLE - Device uses WiFi SAR Configuration Table

SAR 2400 MHz Set1 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5150-5350 MHz Set1 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5350-5470 MHz Set1 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5470-5725 MHz Set1 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5725-5925 MHz Set1 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5945-6165 MHz Set1 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6165-6405 MHz Set1 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6405-6525 MHz Set1 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6525-6705 MHz Set1 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6705-6865 MHz Set1 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6865-7105 MHz Set1 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 2400 MHz Set1 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5150-5350 MHz Set1 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5350-5470 MHz Set1 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5470-5725 MHz Set1 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5725-5925 MHz Set1 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5945-6165 MHz Set1 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6165-6405 MHz Set1 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6405-6525 MHz Set1 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6525-6705 MHz Set1 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6705-6865 MHz Set1 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6865-7105 MHz Set1 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

EWRD Package

WiFi Dynamic SAR

Enable/Disable WiFi Dynamic SAR Tx Power Limit which shell be set dynamically accorting to the Proximity Sensor

Extended SAR Range Sets

Defines the WiFi SAR Sets that can be used to set the power limts dynamically based on the Proximity Sensor,Set 1 is always present if Wifi SAR enabled and Set 2-3 are additinoal sets

SAR 2400 MHz Set2 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5150-5350 MHz Set2 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5350-5470 MHz Set2 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5470-5725 MHz Set2 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5725-5925 MHz Set2 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5945-6165 MHz Set2 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6165-6405 MHz Set2 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6405-6525 MHz Set2 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6525-6705 MHz Set2 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6705-6865 MHz Set2 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6865-7105 MHz Set2 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 2400 MHz Set2 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5150-5350 MHz Set2 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5350-5470 MHz Set2 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5470-5725 MHz Set2 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5725-5925 MHz Set2 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5945-6165 MHz Set2 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6165-6405 MHz Set2 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6405-6525 MHz Set2 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6525-6705 MHz Set2 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6705-6865 MHz Set2 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6865-7105 MHz Set2 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 2400 MHz Set3 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5150-5350 MHz Set3 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5350-5470 MHz Set3 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5470-5725 MHz Set3 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5725-5925 MHz Set3 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5945-6165 MHz Set3 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6165-6405 MHz Set3 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6405-6525 MHz Set3 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6525-6705 MHz Set3 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6705-6865 MHz Set3 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6865-7105 MHz Set3 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 2400 MHz Set3 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5150-5350 MHz Set2 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5350-5470 MHz Set2 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5470-5725 MHz Set2 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5725-5925 MHz Set2 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5945-6165 MHz Set2 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6165-6405 MHz Set2 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6405-6525 MHz Set2 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6525-6705 MHz Set2 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6705-6865 MHz Set2 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6865-7105 MHz Set2 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 2400 MHz Set4 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5150-5350 MHz Set4 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5350-5470 MHz Set4 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5470-5725 MHz Set4 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5725-5925 MHz Set4 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5945-6165 MHz Set4 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6165-6405 MHz Set4 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6405-6525 MHz Set4 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6525-6705 MHz Set4 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6705-6865 MHz Set4 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6865-7105 MHz Set4 Chain A

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 2400 MHz Set4 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5150-5350 MHz Set4 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5350-5470 MHz Set4 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5470-5725 MHz Set4 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5725-5925 MHz Set4 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5945-6165 MHz Set4 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6165-6405 MHz Set4 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6405-6525 MHz Set4 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6525-6705 MHz Set4 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6705-6865 MHz Set4 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6865-7105 MHz Set4 Chain B

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

Antenna A Current Set

Current Set to be used 0 :Default OTP table 1-3 SAR Sets

Antenna B Current Set

Current Set to be used 0 :Default OTP table 1-3 SAR Sets

WGDS Package

SAR 2400 MHz Max Allowed for Group 1 (FCC)

Defines the WiFi SAR Delta Value to be applied - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 2400 MHz Chain A Offset for Group 1 (FCC)

Defines the WiFi SAR Delta Value to be applied - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 2400 MHz Chain B Offset for Group 1 (FCC)

Defines the WiFi SAR Delta Value to be applied - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5200 MHz Max Allowed for Group 1 (FCC)

Defines the WiFi SAR Delta Value to be applied - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5200 MHz Chain A Offset for Group 1 (FCC)

Defines the WiFi SAR Delta Value to be applied - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5200 MHz Chain B Offset for Group 1 (FCC)

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6000-7000 MHz Max Allowed for Group 1 (FCC)

Defines the WiFi SAR Delta Value to be applied - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6000-7000 MHz Chain A Offset for Group 1 (FCC)

Defines the WiFi SAR Delta Value to be applied - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6000-7000 MHz Chain B Offset for Group 1 (FCC)

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 2400 MHz Max Allowed for Group 2 (EU Japan)

Defines the WiFi SAR Delta Value to be applied - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 2400 MHz Chain A Offset for Group 2 (EU Japan)

Defines the WiFi SAR Delta Value to be applied - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 2400 MHz Chain B Offset for Group 2 (EU Japan)

Defines the WiFi SAR Delta Value to be applied - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5200 MHz Max Allowed for Group 2 (EU Japan)

Defines the WiFi SAR Delta Value to be applied - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5200 MHz Chain A Offset for Group 2 (EU Japan)

Defines the WiFi SAR Delta Value to be applied - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5200 MHz Chain B Offset for Group 2 (EU Japan)

Defines the WiFi SAR Delta Value to be applied - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6000-7000 MHz Max Allowed for Group 1 (FCC)

Defines the WiFi SAR Delta Value to be applied - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6000-7000 MHz Chain A Offset for Group 1 (FCC)

Defines the WiFi SAR Delta Value to be applied - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6000-7000 MHz Chain B Offset for Group 1 (FCC)

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 2400 MHz Max Allowed for Group 3 (ROW)

Defines the WiFi SAR Delta Value to be applied - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 2400 MHz Chain A Offset for Group 3 (ROW)

Defines the WiFi SAR Delta Value to be applied - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 2400 MHz Chain B Offset for Group 3 (ROW)

Defines the WiFi SAR Delta Value to be applied - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5200 MHz Max Allowed for Group 3 (ROW)

Defines the WiFi SAR Delta Value to be applied - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5200 MHz Chain A Offset for Group 3 (ROW)

Defines the WiFi SAR Delta Value to be applied - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 5200 MHz Chain B Offset for Group 3 (ROW)

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6000-7000 MHz Max Allowed for Group 1 (FCC)

Defines the WiFi SAR Delta Value to be applied - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6000-7000 MHz Chain A Offset for Group 1 (FCC)

Defines the WiFi SAR Delta Value to be applied - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

SAR 6000-7000 MHz Chain B Offset for Group 1 (FCC)

Defines the WiFi SAR Tx Power Limit - 8bit unsigned with 5bit integer and 3bit fractional. 0x00 = 0b00000000 = 0.125dB; 0xFF = 0b11111111 = 31.875dB. Each step is equivalent to 0.125dB

External 32kHz Clock

This will be used to specify that platform does have valid External 32kHz clock or not..

PPAG Package

Wifi ANT Gain control

Enable / Disable WiFi Antenna Gain control.

ANT Gain 2400MHz Chain A

Defines the WiFi ANT gain Delta Value to be applied - 8bit signed Two's complement 0.125dB. 0x80 = 0b10000000 = -16dB; 0x7F = 0b01111111 = 15.875dB. Each step is equivalent to 0.125dB

ANT Gain 5150MHz-5350MHz Chain A

Defines the WiFi ANT gain Delta Value to be applied - 8bit signed Two's complement 0.125dB. 0x80 = 0b10000000 = -16dB; 0x7F = 0b01111111 = 15.875dB. Each step is equivalent to 0.125dB

Ant Gain 5350MHz-5470MHz Chain A

Defines the WiFi ANT gain Delta Value to be applied - 8bit signed Two's complement 0.125dB. 0x80 = 0b10000000 = -16dB; 0x7F = 0b01111111 = 15.875dB. Each step is equivalent to 0.125dB

Ant Gain 5470MHz-5725MHz Chain A

Defines the WiFi ANT gain Delta Value to be applied - 8bit signed Two's complement 0.125dB. 0x80 = 0b10000000 = -16dB; 0x7F = 0b01111111 = 15.875dB. Each step is equivalent to 0.125dB

Ant Gain 5725MHZ-5945MHz Chain A

Defines the WiFi ANT gain Delta Value to be applied - 8bit signed Two's complement 0.125dB. 0x80 = 0b10000000 = -16dB; 0x7F = 0b01111111 = 15.875dB. Each step is equivalent to 0.125dB

Ant Gain 5945MHZ-6165MHz Chain A

Defines the WiFi ANT gain Delta Value to be applied - 8bit signed Two's complement 0.125dB. 0x80 = 0b10000000 = -16dB; 0x7F = 0b01111111 = 15.875dB. Each step is equivalent to 0.125dB

Ant Gain 6165MHZ-6405MHz Chain A

Defines the WiFi ANT gain Delta Value to be applied - 8bit signed Two's complement 0.125dB. 0x80 = 0b10000000 = -16dB; 0x7F = 0b01111111 = 15.875dB. Each step is equivalent to 0.125dB

Ant Gain 6405MHZ-6525MHz Chain A

Defines the WiFi ANT gain Delta Value to be applied - 8bit signed Two's complement 0.125dB. 0x80 = 0b10000000 = -16dB; 0x7F = 0b01111111 = 15.875dB. Each step is equivalent to 0.125dB

Ant Gain 6525MHZ-6705MHz Chain A

Defines the WiFi ANT gain Delta Value to be applied - 8bit signed Two's complement 0.125dB. 0x80 = 0b10000000 = -16dB; 0x7F = 0b01111111 = 15.875dB. Each step is equivalent to 0.125dB

Ant Gain 6705MHZ-6865MHz Chain A

Defines the WiFi ANT gain Delta Value to be applied - 8bit signed Two's complement 0.125dB. 0x80 = 0b10000000 = -16dB; 0x7F = 0b01111111 = 15.875dB. Each step is equivalent to 0.125dB

Ant Gain 6865MHZ-7105MHz Chain A

Defines the WiFi ANT gain Delta Value to be applied - 8bit signed Two's complement 0.125dB. 0x80 = 0b10000000 = -16dB; 0x7F = 0b01111111 = 15.875dB. Each step is equivalent to 0.125dB

Ant Gain 2400MHz Chain B

Defines the WiFi ANT gain Delta Value to be applied - 8bit signed Two's complement 0.125dB. 0x80 = 0b10000000 = -16dB; 0x7F = 0b01111111 = 15.875dB. Each step is equivalent to 0.125dB

Ant Gain 5150MHz-5350MHz Chain B

Defines the WiFi ANT gain Delta Value to be applied - 8bit signed Two's complement 0.125dB. 0x80 = 0b10000000 = -16dB; 0x7F = 0b01111111 = 15.875dB. Each step is equivalent to 0.125dB

Ant Gain 5350MHz-5470MHz Chain B

Defines the WiFi ANT gain Delta Value to be applied - 8bit signed Two's complement 0.125dB. 0x80 = 0b10000000 = -16dB; 0x7F = 0b01111111 = 15.875dB. Each step is equivalent to 0.125dB

Ant Gain 5470MHz-5725MHz Chain B

Defines the WiFi ANT gain Delta Value to be applied - 8bit signed Two's complement 0.125dB. 0x80 = 0b10000000 = -16dB; 0x7F = 0b01111111 = 15.875dB. Each step is equivalent to 0.125dB

Ant Gain 5725MHZ-5945MHz Chain B

Defines the WiFi ANT gain Delta Value to be applied - 8bit signed Two's complement 0.125dB. 0x80 = 0b10000000 = -16dB; 0x7F = 0b01111111 = 15.875dB. Each step is equivalent to 0.125dB

Ant Gain 5945MHZ-6165MHz Chain B

Defines the WiFi ANT gain Delta Value to be applied - 8bit signed Two's complement 0.125dB. 0x80 = 0b10000000 = -16dB; 0x7F = 0b01111111 = 15.875dB. Each step is equivalent to 0.125dB

Ant Gain 6165MHZ-6405MHz Chain B

Defines the WiFi ANT gain Delta Value to be applied - 8bit signed Two's complement 0.125dB. 0x80 = 0b10000000 = -16dB; 0x7F = 0b01111111 = 15.875dB. Each step is equivalent to 0.125dB

Ant Gain 6405MHZ-6525MHz Chain B

Defines the WiFi ANT gain Delta Value to be applied - 8bit signed Two's complement 0.125dB. 0x80 = 0b10000000 = -16dB; 0x7F = 0b01111111 = 15.875dB. Each step is equivalent to 0.125dB

Ant Gain 6525MHZ-6705MHz Chain B

Defines the WiFi ANT gain Delta Value to be applied - 8bit signed Two's complement 0.125dB. 0x80 = 0b10000000 = -16dB; 0x7F = 0b01111111 = 15.875dB. Each step is equivalent to 0.125dB

Ant Gain 6705MHZ-6865MHz Chain B

Defines the WiFi ANT gain Delta Value to be applied - 8bit signed Two's complement 0.125dB. 0x80 = 0b10000000 = -16dB; 0x7F = 0b01111111 = 15.875dB. Each step is equivalent to 0.125dB

Ant Gain 6865MHZ-7105MHz Chain B

Defines the WiFi ANT gain Delta Value to be applied - 8bit signed Two's complement 0.125dB. 0x80 = 0b10000000 = -16dB; 0x7F = 0b01111111 = 15.875dB. Each step is equivalent to 0.125dB

Bluetooth SAR

Define the mode of SAR control to be used. Disabled: Tx power shall be mandated by device NVM Enabled: Tx power shall be the minimum between BIOS SAR table and BT Device NVM (either Module or Platform)

Bluetooth SAR BR

Defines the SAR power restriction for BR Modulation

Bluetooth SAR EDR2

Defines the SAR power restriction for EDR2 Modulation

Bluetooth SAR EDR3

Defines the SAR power restriction for EDR3 Modulation

Bluetooth SAR LE

Defines the SAR power restriction for LE Modulation

Bluetooth SAR LE 2Mhz

Defines the SAR power restriction for LE 2Mhz Modulation

Bluetooth SAR LE LR

Defines the SAR power restriction for LE LR Modulation

Disable SRD Active Channels

Enable/Disable SRD Active Channels 00 - ETSI 5.8GHz SRD Active Scan Enable 01 - ETSI 5.8GHz SRD Passive Scan Enable 02 - ETSI 5.8GHz SRD Disabled

Supported Indonesia 5.15-5.35 GHz Band

Enable/Disable Indonesia 5.1 00 - Set 5.115-5.35GHz to Disable in Indonesia 01 - Set 5.115-5.35GHz to Enable (Passive) in Indonesia 02 - Reserved

Ultra High Band Support

Enable/Disable UHB support 00 - Disable UHB support 01 - Enable UHB support

WiFi Time Average SAR - WTAS

WTAS Selection

Enable/Disable WTAS

WTAS List Entries

No. of blocked countries not approved by OEM to support this feature.

ISO country code to block

The decimal equivalent of country code (a two-ASCII-character) as specified in ISO_3166-1. Ex. for JP - 19024

ISO country code to block

The decimal equivalent of country code (a two-ASCII-character) as specified in ISO_3166-1. Ex. for JP - 19024

ISO country code to block

The decimal equivalent of country code (a two-ASCII-character) as specified in ISO_3166-1. Ex. for JP - 19024

ISO country code to block

The decimal equivalent of country code (a two-ASCII-character) as specified in ISO_3166-1. Ex. for JP - 19024

ISO country code to block

The decimal equivalent of country code (a two-ASCII-character) as specified in ISO_3166-1. Ex. for JP - 19024

ISO country code to block

The decimal equivalent of country code (a two-ASCII-character) as specified in ISO_3166-1. Ex. for JP - 19024

ISO country code to block

The decimal equivalent of country code (a two-ASCII-character) as specified in ISO_3166-1. Ex. for JP - 19024

ISO country code to block

The decimal equivalent of country code (a two-ASCII-character) as specified in ISO_3166-1. Ex. for JP - 19024

ISO country code to block

The decimal equivalent of country code (a two-ASCII-character) as specified in ISO_3166-1. Ex. for JP - 19024

ISO country code to block

The decimal equivalent of country code (a two-ASCII-character) as specified in ISO_3166-1. Ex. for JP - 19024

ISO country code to block

The decimal equivalent of country code (a two-ASCII-character) as specified in ISO_3166-1. Ex. for JP - 19024

ISO country code to block

The decimal equivalent of country code (a two-ASCII-character) as specified in ISO_3166-1. Ex. for JP - 19024

ISO country code to block

The decimal equivalent of country code (a two-ASCII-character) as specified in ISO_3166-1. Ex. for JP - 19024

ISO country code to block

The decimal equivalent of country code (a two-ASCII-character) as specified in ISO_3166-1. Ex. for JP - 19024

ISO country code to block

The decimal equivalent of country code (a two-ASCII-character) as specified in ISO_3166-1. Ex. for JP - 19024

ISO country code to block

The decimal equivalent of country code (a two-ASCII-character) as specified in ISO_3166-1. Ex. for JP - 19024

WWAN Configuration

WWAN Device

Enable or Disable M.2 WWAN Device

WWAN Reset Workaround

Enabling this workardound will result in BIOS asserting FULL_CARD_POWER_OFF#, PERST# and RESET# WWAN signals before the WWAN Device Power-On Sequence is executed. Disabling it has no impact.

OverClocking Performance Menu

OverClocking Feature

Performance Menu for Processor and Memory.

Per-core HT Disable

Defines the per-core HT disable mask where: 1 - Disable selected logical core HT, 0 - is ignored. Input is in HEX and each bit maps to a logical core. Ex. A value of '1F' would disable HT for cores 4,3,2,1 and 0. Default is 0, all cores have HT enabled. Range is 0 - 0x1FF. You can only disable up to MAX_CORE_COUNT - 1.

Intel Speed Optimizer (ISO)

When enabled Intel Speed Optimizer (ISO) feature will automatically overclocks your processor and depends on Board thermal design. When ISO supported then XTU can change the Core Frequency along with PL1, PL2, and IccMax automatically.

WDT Enable

Enable/Disable WatchDog Timer. Note: This option is ignored on debug BIOS.

BCLK Frequency (pcode) 100.00 MHz

XTU Interface

Enable/Disable XTU Interface. BIOS will only expose XTU interface when enabled.

BCLK Aware Adaptive Voltage

BCLK Aware Adaptive Voltage enable/disable. When enabled, pcode will be aware of the BCLK frequency when calculating the CPU V/F curves. This is ideal for BCLK OC to avoid high voltage overrides. Uses OC Mailbox command 0x15.

Unlimited ICCMAX

Enable/Disable Unlimited ICCMAX. Support VR Current Limit (ICCMAX) value set above 255.75A

PVD Ratio Threshold

Select PVD Ratio Threshold Value from Range 1 to 40. 0 - Auto/Default

PLL Max Banding Ratio

Select PLL Max Banding Ratio Value minimum must be greater than P0 and maximum is 120, when banding ratio below P0 would causing ratio clipping. 0 - Auto (Fused Default)

Vmax Stress

Enable/Disable Vmax Stress feature. Enabled - CPU frequency may be clipped the effective max voltage on the silicon is too high. Disable - CPU frequency will not be clipped if the effective max voltage on the silicon is too high.

Processor

Ring

Uncore

Voltage PLL Trim Controls

Platform Voltage Overrides

Processor

Core Ratio Extension Mode

Enable / Disable Core Ratio Above 85 Extension Mode. Enable - Max Overclocking Ratio Limit as specified by OCMB 0x1 command is 120; Disable - Max Overclocking Ratio Limit as specified by OCMB 0x1 command is 85.

Core Max OC Ratio

Sets the maximum OC Ratio for the CPU Core. Uses Mailbox MSR 0x150, cmd 0x10, 0x11. Range non-turbo max - 85 (Previously max turbo is 83).

Core Max OC Ratio

Sets the maximum OC Ratio for the CPU Core. Uses Mailbox MSR 0x150, cmd 0x10, 0x11. Range non-turbo max - 120 (Previously max turbo is 83).

Per Core Ratio Override

Enable / Disable Per Core Ratio Override. Enable - Set maximum OC ratio to specific core by OCMB 0x1D command; Disable - Set maximum OC ratio to all cores by OCMB command 0x11. Reminding: It's expeced we should manual change the "Turbo Ratio Limit(TRL) MSR 0x1AD / 0x1AE" settings based on here max core ratio changed

Core 0 Max Ratio

Override current maximum OC Ratio for the CPU Core 0.

Core 1 Max Ratio

Override current maximum OC Ratio for the CPU Core 1.

Core 2 Max Ratio

Override current maximum OC Ratio for the CPU Core 2.

Core 3 Max Ratio

Override current maximum OC Ratio for the CPU Core 3.

Core 4 Max Ratio

Override current maximum OC Ratio for the CPU Core 4.

Core 5 Max Ratio

Override current maximum OC Ratio for the CPU Core 5.

Core 6 Max Ratio

Override current maximum OC Ratio for the CPU Core 6.

Core 7 Max Ratio

Override current maximum OC Ratio for the CPU Core 7.

Core 8 Max Ratio

Override current maximum OC Ratio for the CPU Core 8.

Core 9 Max Ratio

Override current maximum OC Ratio for the CPU Core 9.

Core Voltage Mode

Selects between Adaptive and Override Voltage modes. In Override Mode the voltage selected will be applied over all operating frequencies. In Adaptive Mode the voltage is interpolated only in turbo mode. Uses Mailbox MSR 0x150, cmd 0x10, 0x11.

Core Voltage Override

Specifies the Override Voltage applied to the IA Core domain. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11. Range 0-2000 mV.

Core Extra Turbo Voltage

Specifies the extra turbo voltage applied while IA Core is operating in turbo mode. Uses Mailbox MSR 0x150, cmd 0x10, 0x11. Range 0-2000 mV

VF Offset Mode

Selects between Legacy and Selection modes. Need Reset System after enabling OverClocking Feature to Initialize the default value. In Legacy Mode, setting a global offset for the entire VF curve. In Selection modes, setting a selected VF point.

VF Configuration Scope

Alows both all cores VF curve or per-core VF curve configuration.

Core Voltage Offset

Specifies the Offset Voltage applied to the Global IA Core domain. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11. Range -500 to 500 mV

Offset Prefix

Sets the offset value as positive or negative.

Core 0 Voltage Offset

Specifies the Offset Voltage applied to the IA Core 0 domain. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11. Range -500 to 500 mV

Offset Prefix

Sets the offset value as positive or negative.

Core 1 Voltage Offset

Specifies the Offset Voltage applied to the IA Core 1 domain. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11. Range -500 to 500 mV

Offset Prefix

Sets the offset value as positive or negative.

Core 2 Voltage Offset

Specifies the Offset Voltage applied to the IA Core 2 domain. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11. Range -500 to 500 mV

Offset Prefix

Sets the offset value as positive or negative.

Core 3 Voltage Offset

Specifies the Offset Voltage applied to the IA Core 3 domain. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11. Range -500 to 500 mV

Offset Prefix

Sets the offset value as positive or negative.

Core 4 Voltage Offset

Specifies the Offset Voltage applied to the IA Core 4 domain. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11. Range -500 to 500 mV

Offset Prefix

Sets the offset value as positive or negative.

Core 5 Voltage Offset

Specifies the Offset Voltage applied to the IA Core 5 domain. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11. Range -500 to 500 mV

Offset Prefix

Sets the offset value as positive or negative.

Core 6 Voltage Offset

Specifies the Offset Voltage applied to the IA Core 6 domain. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11. Range -500 to 500 mV

Offset Prefix

Sets the offset value as positive or negative.

Core 7 Voltage Offset

Specifies the Offset Voltage applied to the IA Core 7 domain. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11. Range -500 to 500 mV

Offset Prefix

Sets the offset value as positive or negative.

VF Point 1 Offset

Specifies the Offset Voltage applied to the Selected VF Point 1. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11, Param1 0:Core 2:Ring, Param2 0x1. Range -500 to 500 mV

VF Point 1 Offset Prefix

Sets the offset value as positive or negative.

VF Point 1 Ratio N/A

VF Point 2 Offset

Specifies the Offset Voltage applied to the Selected VF Point 2. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11, Param1 0:Core 2:Ring, Param2 0x2. Range -500 to 500 mV

VF Point 2 Offset Prefix

Sets the offset value as positive or negative.

VF Point 2 Ratio N/A

VF Point 3 Offset

Specifies the Offset Voltage applied to the Selected VF Point 3. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11, Param1 0:Core 2:Ring, Param2 0x3. Range -500 to 500 mV

VF Point 3 Offset Prefix

Sets the offset value as positive or negative.

VF Point 3 Ratio N/A

VF Point 4 Offset

Specifies the Offset Voltage applied to the Selected VF Point 4. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11, Param1 0:Core 2:Ring, Param2 0x4. Range -500 to 500 mV

VF Point 4 Offset Prefix

Sets the offset value as positive or negative.

VF Point 4 Ratio N/A

VF Point 5 Offset

Specifies the Offset Voltage applied to the Selected VF Point 5. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11, Param1 0:Core 2:Ring, Param2 0x5. Range -500 to 500 mV

VF Point 5 Offset Prefix

Sets the offset value as positive or negative.

VF Point 5 Ratio N/A

VF Point 6 Offset

Specifies the Offset Voltage applied to the Selected VF Point 6. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11, Param1 0:Core 2:Ring, Param2 0x6. Range -500 to 500 mV

VF Point 6 Offset Prefix

Sets the offset value as positive or negative.

VF Point 6 Ratio N/A

VF Point 7 Offset

Specifies the Offset Voltage applied to the Selected VF Point 7. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11, Param1 0:Core 2:Ring, Param2 0x7. Range -500 to 500 mV

VF Point 7 Offset Prefix

Sets the offset value as positive or negative.

VF Point 7 Ratio N/A

VF Point 8 Offset

Specifies the Offset Voltage applied to the Selected VF Point 8. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11, Param1 0:Core 2:Ring, Param2 0x8. Range -500 to 500 mV

VF Point 8 Offset Prefix

Sets the offset value as positive or negative.

VF Point 8 Ratio N/A

VF Point 9 Offset

Specifies the Offset Voltage applied to the Selected VF Point 9. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11, Param1 0:Core 2:Ring, Param2 0x9. Range -500 to 500 mV

VF Point 9 Offset Prefix

Sets the offset value as positive or negative.

VF Point 9 Ratio N/A

VF Point 10 Offset

Specifies the Offset Voltage applied to the Selected VF Point 10. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11, Param1 0:Core 2:Ring, Param2 0xA. Range -500 to 500 mV

VF Point 10 Offset Prefix

Sets the offset value as positive or negative.

VF Point 10 Ratio N/A

VF Point 11 Offset

Specifies the Offset Voltage applied to the Selected VF Point 11. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11, Param1 0:Core 2:Ring, Param2 0xB. Range -500 to 500 mV

VF Point 11 Offset Prefix

Sets the offset value as positive or negative.

VF Point 11 Ratio N/A

VF Point 12 Offset

Specifies the Offset Voltage applied to the Selected VF Point 12. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11, Param1 0:Core 2:Ring, Param2 0xC. Range -500 to 500 mV

VF Point 12 Offset Prefix

Sets the offset value as positive or negative.

VF Point 12 Ratio N/A

VF Point 13 Offset

Specifies the Offset Voltage applied to the Selected VF Point 13. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11, Param1 0:Core 2:Ring, Param2 0xD. Range -500 to 500 mV

VF Point 13 Offset Prefix

Sets the offset value as positive or negative.

VF Point 13 Ratio N/A

VF Point 14 Offset

Specifies the Offset Voltage applied to the Selected VF Point 14. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11, Param1 0:Core 2:Ring, Param2 0xE. Range -500 to 500 mV

VF Point 14 Offset Prefix

Sets the offset value as positive or negative.

VF Point 14 Ratio N/A

VF Point 15 Offset

Specifies the Offset Voltage applied to the Selected VF Point 15. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11, Param1 0:Core 2:Ring, Param2 0xF. Range -500 to 500 mV

Sets the offset value as positive or negative.

VF Point 15 Ratio N/A

AVX2 Ratio Offset

AVX2 Ratio Offset. Specifies number of bins to decrease AVX ratio vs. Core Ratio. AVX is a more stressful workload, it is helpful to lower the AVX ratio to ensure maximum possible ratio for SSE workloads. Uses Mailbox MSR 0x150, cmd 0x1B. Range 0 - 31. 0 = No offset.

AVX2 Voltage Guardband Scale Factor

AVX2 Voltage Guardband Scale Factor. Controls the voltage guardband applied to AVX workloads. Range 0 - 200 in 1/100 units, where 125 = 1.25 scale factor. Default = 0, no scale factor applied. A value of 100 applies the default voltage guardband scale factor of 1.0. A value > 100 will increase the votlage guardband, and < 100 will decrease the voltage guardband.

AVX512 Ratio Offset

AVX512 Ratio Offset. Specifies number of bins to decrease AVX ratio vs. Core Ratio. AVX is a more stressful workload, it is helpful to lower the AVX ratio to ensure maximum possible ratio for SSE workloads. Uses Mailbox MSR 0x150, cmd 0x1B. Range 0 - 31. 0 = No offset.

AVX512 Voltage Guardband Scale Factor

AVX512 Voltage Guardband Scale Factor. Controls the voltage guardband applied to AVX workloads. Range 0 - 200 in 1/100 units, where 125 = 1.25 scale factor. Default = 0, no scale factor applied. A value of 100 applies the default voltage guardband scale factor of 1.0. A value > 100 will increase the votlage guardband, and < 100 will decrease the voltage guardband.

TjMax Offset

TjMax Offset. Specified value here is clipped by pCode (125 - TjMax Offset) to support TjMax in the range of 62 to 115 deg Celsius. Uses Mailbox MSR 0x37, command 0x01. Range 10 - 63. 0 = No offset.

Thermal Velocity Boost (TVB)

TVB Ratio Clipping

This service controls Core frequency reduction caused by high package temperatures for processors that implement the Intel Thermal Velocity Boost (TVB) feature. It is required to be disabled for supporting overclocking at frequencies higher than the default max turbo frequency. Default is disabled. Uses Overclocking Mailbox command 0x18/0x19.

TVB Voltage Optimizations

This service controls thermal based voltage optimizations for processors that implement the Intel Thermal Velocity Boost (TVB) feature. Default is enabled. Uses Overclocking Mailbox command 0x18/0x19.

Expected CPU Freq

Expected Processor frequency calculated using Bus ratio and Bus speed.

Ring

Ring Max OC Ratio

Sets the maximum OC Ratio for the CPU Ring. Uses Mailbox MSR 0x150, cmd 0x10, 0x11. Range non-turbo max - 85.

Ring Voltage Mode

Ring Voltage Override

Specifies the Override Voltage applied to the Ring domain. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11. Range 0-2000 mV.

Ring Extra Turbo Voltage

Specifies the extra turbo voltage applied while ring is operating in turbo mode. Uses Mailbox MSR 0x150, cmd 0x10, 0x11. Range 0-2000 mV

VF Offset Mode

Ring Voltage Offset

Specifies the Offset Voltage applied to the Ring domain. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11. Range -500 to 500 mV

Offset Prefix

Sets the offset value as positive or negative.

VF Point 1 Offset

Specifies the Offset Voltage applied to the Selected VF Point 1. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11, Param1 0:Core 2:Ring, Param2 0x1. Range -500 to 500 mV

VF Point 1 Offset Prefix

Sets the offset value as positive or negative.

VF Point 1 Ratio N/A

VF Point 2 Offset

Specifies the Offset Voltage applied to the Selected VF Point 2. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11, Param1 0:Core 2:Ring, Param2 0x2. Range -500 to 500 mV

VF Point 2 Offset Prefix

Sets the offset value as positive or negative.

VF Point 2 Ratio N/A

VF Point 3 Offset

Specifies the Offset Voltage applied to the Selected VF Point 3. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11, Param1 0:Core 2:Ring, Param2 0x3. Range -500 to 500 mV

VF Point 3 Offset Prefix

Sets the offset value as positive or negative.

VF Point 3 Ratio N/A

VF Point 4 Offset

Specifies the Offset Voltage applied to the Selected VF Point 4. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11, Param1 0:Core 2:Ring, Param2 0x4. Range -500 to 500 mV

VF Point 4 Offset Prefix

Sets the offset value as positive or negative.

VF Point 4 Ratio N/A

VF Point 5 Offset

Specifies the Offset Voltage applied to the Selected VF Point 5. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11, Param1 0:Core 2:Ring, Param2 0x5. Range -500 to 500 mV

VF Point 5 Offset Prefix

Sets the offset value as positive or negative.

VF Point 5 Ratio N/A

VF Point 6 Offset

Specifies the Offset Voltage applied to the Selected VF Point 6. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11, Param1 0:Core 2:Ring, Param2 0x6. Range -500 to 500 mV

VF Point 6 Offset Prefix

Sets the offset value as positive or negative.

VF Point 6 Ratio N/A

VF Point 7 Offset

Specifies the Offset Voltage applied to the Selected VF Point 7. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11, Param1 0:Core 2:Ring, Param2 0x7. Range -500 to 500 mV

VF Point 7 Offset Prefix

Sets the offset value as positive or negative.

VF Point 7 Ratio N/A

VF Point 8 Offset

Specifies the Offset Voltage applied to the Selected VF Point 8. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11, Param1 0:Core 2:Ring, Param2 0x8. Range -500 to 500 mV

VF Point 8 Offset Prefix

Sets the offset value as positive or negative.

VF Point 8 Ratio N/A

VF Point 9 Offset

Specifies the Offset Voltage applied to the Selected VF Point 9. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11, Param1 0:Core 2:Ring, Param2 0x9. Range -500 to 500 mV

VF Point 9 Offset Prefix

Sets the offset value as positive or negative.

VF Point 9 Ratio N/A

VF Point 10 Offset

Specifies the Offset Voltage applied to the Selected VF Point 10. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11, Param1 0:Core 2:Ring, Param2 0xA. Range -500 to 500 mV

VF Point 10 Offset Prefix

Sets the offset value as positive or negative.

VF Point 10 Ratio N/A

VF Point 11 Offset

Specifies the Offset Voltage applied to the Selected VF Point 11. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11, Param1 0:Core 2:Ring, Param2 0xB. Range -500 to 500 mV

VF Point 11 Offset Prefix

Sets the offset value as positive or negative.

VF Point 11 Ratio N/A

VF Point 12 Offset

Specifies the Offset Voltage applied to the Selected VF Point 12. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11, Param1 0:Core 2:Ring, Param2 0xC. Range -500 to 500 mV

VF Point 12 Offset Prefix

Sets the offset value as positive or negative.

VF Point 12 Ratio N/A

VF Point 13 Offset

Specifies the Offset Voltage applied to the Selected VF Point 13. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11, Param1 0:Core 2:Ring, Param2 0xD. Range -500 to 500 mV

VF Point 13 Offset Prefix

Sets the offset value as positive or negative.

VF Point 13 Ratio N/A

VF Point 14 Offset

Specifies the Offset Voltage applied to the Selected VF Point 14. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11, Param1 0:Core 2:Ring, Param2 0xE. Range -500 to 500 mV

VF Point 14 Offset Prefix

Sets the offset value as positive or negative.

VF Point 14 Ratio N/A

VF Point 15 Offset

Specifies the Offset Voltage applied to the Selected VF Point 15. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11, Param1 0:Core 2:Ring, Param2 0xF. Range -500 to 500 mV

Sets the offset value as positive or negative.

VF Point 15 Ratio N/A

Ring Down Bin

Enable/Disable Ring Downbin feature. Enabled - CPU will down bin the ring ratio, which means the requested max ring ratio will not be observed. Disable - CPU will not down bin the ring ratio and the requested ring ratio limit will be observed. Default for Overclocking is "Disabled" to allow for a predictable ring ratio. Uses OC mailbox command 0x19.

Min Ring Ratio Limit

This sets the minimum ring ratio limit. 0 - Auto/HW default. 1-LFM are invalid ratio settings.

Max Ring Ratio Limit

This sets the maximum ring ratio limit. 0 - Auto/HW default. 1-LFM are invalid ratio settings.

GT Domain

GT OverClocking Frequency

Overclocked RP0 Frequency (MLC Clk) in multiples of 50 MHz

GT Voltage Mode

GT Voltage Override

Specifies the Override Voltage applied to the GT domain. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11. Range 0-2000 mV

GT Extra Turbo Voltage

Specifies the extra turbo voltage applied while GT is operating in turbo mode. Unit is in millivolts. Uses Mailbox MSR 0x150, cmd 0x11. Range 0-2000 mV

GT Voltage Offset

Specifies the Offset Voltage applied to the GT domain. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11. Range -1000 to 1000 mV

Offset Prefix

Sets the offset value as positive or negative.

GT Unslice Domain

GT OverClocking Frequency

Overclocked RP0 Frequency (MLC Clk) in multiples of 50 MHz

GT Voltage Mode

GT Voltage Override

Specifies the Override Voltage applied to the GT domain. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11. Range 0-2000 mV

GT Extra Turbo Voltage

Specifies the extra turbo voltage applied while GT is operating in turbo mode. Unit is in millivolts. Uses Mailbox MSR 0x150, cmd 0x11. Range 0-2000 mV

GTU Voltage Offset

Specifies the Offset Voltage applied to the GT domain. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11. Range -1000 to 1000 mV

Offset Prefix

Sets the offset value as positive or negative.

Uncore

Uncore Voltage Mode

Uncore Voltage Override

Specifies the Override Voltage applied to the SA Uncore domain. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11. Range 0-2000 mV.

Uncore Extra Turbo Voltage

Specifies the extra turbo voltage applied while SA Uncore is operating in turbo mode. Uses Mailbox MSR 0x150, cmd 0x10, 0x11. Range 0-2000 mV

Uncore Voltage Offset

Specifies the Offset Voltage applied to the Uncore domain. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11. Range -1000 to 1000 mV

Offset Prefix

Sets the offset value as positive or negative.

Platform Voltage Overrides

VccCore Override Enable

Overrides the VccCore voltage using SMBUS/PMBUS interface of VRM. Use the next option for exact voltage configuration

VccCore

Range of VccCore voltage - Up to 2550 mV. Default is 1300 mV

VccST Override Enable

Overrides the VccST voltage using SMBUS/PMBUS interface of VRM. Use the next option for exact voltage configuration

VccST

Range of VccST voltage - 250 mV to 1500 mV. Default is 1020 mV

VccSA Override Enable

Overrides the VccSA voltage using SMBUS/PMBUS interface of VRM. Use the next option for exact voltage configuration

VccSA

Range of VccSA voltage - Up to 1500 mV. Default is 1050 mV

VccSFR_OC Override Enable

Overrides the VccSFR_OC voltage using SMBUS/PMBUS interface of VRM. Use the next option for exact voltage configuration

VccSFR_OC

Range of VccSFR_OC voltage range - 1000mV to 2520mV. Default is 1250mV

VccSFR Override Enable

Overrides the VccSFR voltage using SMBUS/PMBUS interface of VRM. Use the next option for exact voltage configuration

VccSFR

Range of VccSFR voltage - 690mV to 2050mV. Default is 1020mV

VccIO Override Enable

Overrides the VccIO voltage using SMBUS/PMBUS interface of VRM. Use the next option for exact voltage configuration

VccIO

Range of VccIO voltage - 900 mV to 1520 mV. Default for CML CPU is 950 mV and for RKL CPU is 1050mV

Core VR Loadline Override

Overrides the Core VR DC Loadline. Use the next option for exact voltage configuration

DC Loadline value

DC Loadline value as 2100 then override matches to 0xC produces the same value as without override (2.1mOhm).

Voltage PLL Trim Controls

Core PLL Voltage Offset

PLL Voltage Offset, CML Range 0-63 and RKL Range 0-15. Units are in 17.5mV. Default is 0. This control can be used to increase the range of this domain frequency in extreme overclocking conditions.

GT PLL Voltage Offset

PLL Voltage Offset, CML Range 0-63 and RKL Range 0-15. Units are in 17.5mV. Default is 0. This control can be used to increase the range of this domain frequency in extreme overclocking conditions.

Ring PLL Voltage Offset

PLL Voltage Offset, CML Range 0-63 and RKL Range 0-15. Units are in 17.5mV. Default is 0. This control can be used to increase the range of this domain frequency in extreme overclocking conditions.

System Agent PLL Voltage Offset

PLL Voltage Offset, CML Range 0-63 and RKL Range 0-15. Units are in 17.5mV. Default is 0. This control can be used to increase the range of this domain frequency in extreme overclocking conditions.

Memory Controller PLL Voltage Offset

PLL Voltage Offset, CML Range 0-63 and RKL Range 0-15. Units are in 17.5mV. Default is 0. This control can be used to increase the range of this domain frequency in extreme overclocking conditions.

Voltage PLL Trim Controls

Core PLL Voltage Offset

PLL Voltage Offset, CML Range 0-63 and RKL Range 0-15. Units are in 17.5mV. Default is 0. This control can be used to increase the range of this domain frequency in extreme overclocking conditions.

GT PLL Voltage Offset

PLL Voltage Offset, CML Range 0-63 and RKL Range 0-15. Units are in 17.5mV. Default is 0. This control can be used to increase the range of this domain frequency in extreme overclocking conditions.

Ring PLL Voltage Offset

PLL Voltage Offset, CML Range 0-63 and RKL Range 0-15. Units are in 17.5mV. Default is 0. This control can be used to increase the range of this domain frequency in extreme overclocking conditions.

System Agent PLL Voltage Offset

PLL Voltage Offset, CML Range 0-63 and RKL Range 0-15. Units are in 17.5mV. Default is 0. This control can be used to increase the range of this domain frequency in extreme overclocking conditions.

Memory Controller PLL Voltage Offset

PLL Voltage Offset, CML Range 0-63 and RKL Range 0-15. Units are in 17.5mV. Default is 0. This control can be used to increase the range of this domain frequency in extreme overclocking conditions.

PCI Express Gen3 Configuration

PEG Port Configuration

Gen3 RxCTLE Control

Gen3 Adaptive Software Equalization

DMI Link ASPM Control

Enable/Disable the control of Active State Power Management on SA side of the DMI Link.

Always Attempt SW EQ

Always Attempt SW EQ, even it has been done once

Number of Presets to test

Choose between 7,3,5,8 and 0-9. Auto = current default (7,3,5,8) Do not change from the default unless debugging.

Allow PERST# GPIO Usage

Enable/Disable GPIO-based resets to PEG endpoint(s) during margin search, if needed

SW EQ Enable VOC

Select Jitter & VOC test mode (default) or Jitter only test mode. Auto will current default (Enabled)

Jitter Dwell Time

PEG Gen3 Preset Search dwell time [0..65535] in [usec]

Jitter Error Target

The margin search error target value [1..65535]

VOC Dwell Time

The VOC margin search dwell time [0..65535] in [usec]

VOC Error Target

The VOC margin search error target value [1..65535]

Generate BDAT PEG Margin Data

Enable to generate BDAT PCIe margin tables

PEG IMR

Enable/Disable PEG IMR PCIe IMR can either be enabled on the SA or PCH but not both simultaneously

PEG IMR Size

PEG Reserved Memory Size to be requested in MB. Maximum value of 1024 MB Value should be 2 power N, where N=0 to 10

RP index for IMR

Selects which root port will be associated with IMR

PCIe Rx CEM Test Mode

Enable/Disable PEG Rx CEM Loopback Mode

PEG Lane number for Test

PEG Lane number for Rx CEM Loopback mode (0 ~ 15)

Non-Protocol Awareness

Enable/Disable Non-Protocol Awareness

PCIe Spread Spectrum Clocking

Allows disableing Spread Spectrum Clocking for compliance testing

PEG Port Configuration

PEG 0:1:0 Not Present

Max Link Speed

Configure PEG 0:1:0 Max Speed

Max Link Width

Force PEG link to retrain to X1/2/4/8

Gen3 Eq Phase 2

Perform Gen3 Equalization Phase 2

Gen3 Eq Phase 3 Method

Select Method for Gen3 Equalization Phase 3

ASPM L0s

PEG0: Enable PCIe ASPM L0s.

De-emphasis Control

PEG0: Configure the De-emphasis control on PEG

PEG0 Slot Power Limit Value

Sets the upper limit on power supplied by slot. Power limit (in Watts) is calculated by multiplying this value by the Slot Power Limit Scale. Values 0-255

PEG0 Slot Power Limit Scale

Select the scale used for the Slot Power Limit Value.

PEG0 Physical Slot Number

Set the physical slot number attached to this Port. The number has to be globally unique within the chassis. Values 0-8191

PEG 0:1:1 Not Present

Max Link Speed

Configure PEG 0:1:1 Max Speed

Max Link Width

Force PEG link to retrain to X1/2/4/8

Gen3 Eq Phase 2

Perform Gen3 Equalization Phase 2

Gen3 Eq Phase 3 Method

Select Method for Gen3 Equalization Phase 3

ASPM L0s

PEG1: Enable PCIe ASPM L0s.

De-emphasis Control

PEG1: Configure the De-emphasis control on PEG

PEG1 Slot Power Limit Value

Sets the upper limit on power supplied by slot. Power limit (in Watts) is calculated by multiplying this value by the Slot Power Limit Scale. Values 0-255

PEG1 Slot Power Limit Scale

Select the scale used for the Slot Power Limit Value.

PEG1 Physical Slot Number

Set the physical slot number attached to this Port. The number has to be globally unique within the chassis. Values 0-8191

PEG 0:1:2 Not Present

Max Link Speed

Configure PEG 0:1:2 Max Speed

Max Link Width

Force PEG link to retrain to X1/2/4/8

Gen3 Eq Phase 2

Perform Gen3 Equalization Phase 2

Gen3 Eq Phase 3 Method

Select Method for Gen3 Equalization Phase 3

ASPM L0s

PEG2: Enable PCIe ASPM L0s.

De-emphasis Control

PEG2: Configure the De-emphasis control on PEG

PEG2 Slot Power Limit Value

Sets the upper limit on power supplied by slot. Power limit (in Watts) is calculated by multiplying this value by the Slot Power Limit Scale. Values 0-255

PEG2 Slot Power Limit Scale

Select the scale used for the Slot Power Limit Value.

PEG2 Physical Slot Number

Set the physical slot number attached to this Port. The number has to be globally unique within the chassis. Values 0-8191

PEG 0:6:0 Not Present

Max Link Speed

Configure PEG 0:6:0 Max Speed

Max Link Width

Force PEG link to retrain to X1/2/4/8

Gen3 Eq Phase 2

Perform Gen3 Equalization Phase 2

Gen3 Eq Phase 3 Method

Select Method for Gen3 Equalization Phase 3

ASPM L0s

PEG3: Enable PCIe ASPM L0s.

De-emphasis Control

PEG3: Configure the De-emphasis control on PEG

PEG3 Slot Power Limit Value

Sets the upper limit on power supplied by slot. Power limit (in Watts) is calculated by multiplying this value by the Slot Power Limit Scale. Values 0-255

PEG3 Slot Power Limit Scale

Select the scale used for the Slot Power Limit Value.

PEG3 Physical Slot Number

Set the physical slot number attached to this Port. The number has to be globally unique within the chassis. Values 0-8191

Gen3 RxCTLE Control

Bundle0

Gen3 RxCTLE setting for Bundle0 (Lane0, Lane1)

Bundle1

Gen3 RxCTLE setting for Bundle1 (Lane2, Lane3)

Bundle2

Gen3 RxCTLE setting for Bundle2 (Lane4, Lane5)

Bundle3

Gen3 RxCTLE setting for Bundle3 (Lane6, Lane7)

Bundle4

Gen3 RxCTLE setting for Bundle4 (Lane8, Lane9)

Bundle5

Gen3 RxCTLE setting for Bundle5 (Lane10, Lane11)

Bundle6

Gen3 RxCTLE setting for Bundle6 (Lane12, Lane13)

Bundle7

Gen3 RxCTLE setting for Bundle7 (Lane14, Lane15)

PEG10 RxCTLE Override

When Enabled, it overrides PEG0 RxCTLE adaptive behavior

PEG11 RxCTLE Override

When Enabled, it overrides PEG1 RxCTLE adaptive behavior

PEG12 RxCTLE Override

When Enabled, it overrides PEG2 RxCTLE adaptive behavior

PEG60 RxCTLE Override

When Enabled, it overrides PEG3 RxCTLE adaptive behavior

DMI RxCTLE Override

When Enabled, it overrides DMI RxCTLE adaptive behavior

Memory Thermal Configuration

Memory Training Algorithms

Memory

Memory Configuration

Memory RC Version N/A

Memory Frequency N/A

Memory Timings (tCL-tRCD-tRP-tRAS) N/A

Channel 0 Slot 0 N/A

Size N/A

Number of Ranks N/A

Manufacturer UnKnown

Channel 0 Slot 1 N/A

Size N/A

Number of Ranks N/A

Manufacturer UnKnown

Channel 1 Slot 0 N/A

Size N/A

Number of Ranks N/A

Manufacturer UnKnown

Channel 1 Slot 1 N/A

Size N/A

Number of Ranks N/A

Manufacturer UnKnown

MRC ULT Safe Config

MRC ULT Safe Config for PO

Safe Mode Support

Safe Mode enable support. Option will be used for changes/WAs that may affect an stable MRC

Maximum Memory Frequency

Maximum Memory Frequency in Mhz. Must divide by 133 or 100 according to the refclk. In Gear2 must divide by 266 or 200. Lowest Gear2 speed is 2133

HOB Buffer Size

Size to set HOB Buffer

ECC Support

Enable/disable DDR Ecc Support

Max TOLUD

Maximum Value of TOLUD. Dynamic assignment would adjust TOLUD automatically based on largest MMIO length of installed graphic controller

DDR Speed Control

DDR Frequency and Gear1 / Gear2 control for all SAGV points

SA GV Low Freq

System Agent Geyserville. Set frequency for low point. Default 1067 for LPDDR4, 1333 for DDR4. Must be the lowest frequency.

SA GV Mid Freq

System Agent Geyserville. Set frequency for mid point. Default 1867. Must be Low <= Mid <= High

SA GV Low Gear

Gear Selection for SAGV Low point

SA GV Mid Gear

Gear Selection for SAGV Mid point

SA GV High Gear

Gear Selection for SAGV High point, or when SAGV is disabled

Retrain on Fast Fail

Restart MRC in Cold mode if SW MemTest fails during Fast flow. Default = Enabled

DDR4_1DPC

DDR4 1DPC performance feature for 2R DIMMs. Can be enabled on DIMM0 or DIMM1 only, or on both

Enable RH Prevention

Actively prevent Row Hammer

Row Hammer Solution

Type of method used to prevent Row Hammer

RH Activation Probability

Used to adjust MC for Hardware RHP.

Exit On Failure (MRC)

Exit On Failure for MRC training steps

Probeless Trace

Enable/Disable capacity to activate Probeless Trace feature.

Ch Hash Support

Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode

Ch Hash Mask

Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to BITS [19:6}

Ch Hash Interleaved Bit

Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8

Extended Bank Hashing

Per Bank Refresh

Enables and Disables the per bank refresh. This only impacts memory technologies that support PBR: LPDDR3, LPDDR4.

Power Down Mode

CKE Power Down Mode Control

Pwr Down Idle Timer

The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means AUTO: 64 for ULX/ULT, 128 for DT/Halo

Memory Scrambler

Enable/Disable Memory Scrambler support.

Force ColdReset

Force ColdReset OR Choose MrcColdBoot mode, when Coldboot is required during MRC execution. Note: If ME 5.0MB is present, ForceColdReset is required!

Channel A DIMM Control

Channel A DIMM Control Support - Enable or Disable Dimms on Channel A.

Channel B DIMM Control

Channel B DIMM Control Support - Enable or Disable Dimms on Channel B.

Force Single Rank

When enabled, only Rank 0 will be used in each DIMM

Memory Remap

Enable/Disable Memory Remap above 4GB

Time Measure

Enable/Disable printing of the time it takes to execute MRC.

Fast Boot

Enable/Disable fast path thru the MRC

Train On Warm boot

Enable/Disable training on warm boot

Rank Margin Tool Per Task

Enables/Disables RMT running at every major training step

Training Tracing

Enables/Disables printing of the current trained state at every major training step.

Lpddr Mem WL Set

Only applicable to LPDDR, Memory Write Latency Set selection (A is default, B will be used if memory devices support it)

BDAT Memory Test Type

Indicates the type of Memory Training data to populate into the BDAT ACPI table.

Rank Margin Tool Loop Count

Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO

Low Supply for LPDDR4 Data

Low Supply for LPDDR4 Clock/Command/Control

Memory Test on Warm Boot

Enable Or Disable Base Memory Test Run on Warm Boot

System Agent (SA) Configuration

SA PCIe Code Version N/A

VT-d N/A

Graphics Configuration

DMI/OPI Configuration

PEG Port Configuration

VMD setup menu

Display setup menu

PCI Express Configuration

PCI Express Gen3 Configuration

Stop Grant Configuration

Automatic/Manual stop grant configuration

Number of Stop Grant Cycles

Selects number of Stop-Grant cycles.

VT-d

VT-d capability

X2APIC Opt Out

Enable/Disable X2APIC_OPT_OUT bit

DMA Control Guarantee

Enable/Disable DMA_CONTROL_GUARANTEE bit

IGD VTD Enable

Enable/Disable IGD VTD

IOP VTD Enable

Enable/Disable IOP VTD

CHAP Device (B0:D7:F0)

Enable/Disable SA CHAP Device.

Thermal Device (B0:D4:F0)

Enable/Disable SA Thermal Device. Always enabled for ICL A0 stepping.

Cpu CrashLog (Device 10)

Enable/Disable Cpu CrashLog Device.

GNA Device (B0:D8:F0)

Enable/Disable SA GNA Device.

CRID Support

Enable/Disable SA CRID and TCSS CRID control for Intel SIPP

Above 4GB MMIO BIOS assignment

Enable/Disable above 4GB MemoryMappedIO BIOS assignment This is enabled automatically when Aperture Size is set to 2048MB.

MIPI Camera Configuration

eDRAM Mode

SW Mode eDRAM On or eDRAM Off

Memory Profile: Default Custom XMP1 XMP2

tCK [MHz] 0000000 0000000 0000000 0000000

tCL 00000 00000 00000 00000

tRCD/tRP 00000 00000 00000 00000

tRAS 00000 00000 00000 00000

tCWL 00000 00000 00000 00000

tFAW 00000 00000 00000 00000

tREFI 00000 00000 00000 00000

tRFC 00000 00000 00000 00000

tRRD 00000 00000 00000 00000

tRTP 00000 00000 00000 00000

tWR 00000 00000 00000 00000

tWTR 00000 00000 00000 00000

NMode 00000 00000 00000 00000

VDD [mV] 00000 00000 00000 00000

Realtime Memory Timing

Enable/Disable realtime memory timings. When enabled, the system will allow performing realtime memory timing changes after MRC_DONE.

Memory profile

Select DIMM timing profile. The below values start with the currently running values and don't auto populate.

Realtime Memory OverClock

This will automatically train the XMP1 Profile and allow toggling between module default frequency and XMP1 frequency in real-time.

Memory Reference Clock

100MHz, 133MHz.

Memory Ratio

0 = Auto, or the frequency will equal ratio times reference clock. Set to 0 (Auto) to recalculate memory timings listed below.

QCLK Odd Ratio

Adds 133 or 100 MHz to QCLK frequency, depending on RefClk

tCL

CAS Latency, 0: AUTO, max: 31

tRCD/tRP

RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63

tRAS

RAS Active Time, 0: AUTO, max: 64

tCWL

Min CAS Write Latency Delay Time, 0: AUTO, max: 20

tFAW

Min Four Activate Window Delay Time, 0: AUTO, max: 63

tREFI

Refresh Interval, 0: AUTO, max: 65535

tRFC

Min Refresh Recovery Delay Time, 0: AUTO, max: 1023

tRRD

Min Row Active to Row Active Delay Time, 0: AUTO, max: 31

tRTP

Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal values: 5, 6, 7, 8, 9, 10, 12

tWR

Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24

tWTR

Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28

NMode

System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N

Memory Voltage

Memory Voltage Override (Vddq). Default = no override

DllBwEn[0]

DllBwEn[0], for 1067 (0..7)

DllBwEn[1]

DllBwEn[1], for 1333 (0..7)

DllBwEn[2]

DllBwEn[2], for 1600 (0..7)

DllBwEn[3]

DllBwEn[3], for 1867 and up (0..7)

VDD N/A

Graphics Configuration

Graphics Turbo IMON Current

Graphics turbo IMON current values supported (14-31)

Skip Scaning of External Gfx Card

If Enable, it will not scan for External Gfx Card on PEG and PCH PCIE Ports

Primary Display

Select which of IGFX/PEG/PCI Graphics device should be Primary Display Or select HG for Hybrid Gfx.

Select PCIE Card

Select the card used on the platform Auto : Skip GPIO based Power Enable to dGPU Elk Creek 4: DGPU Power Enable = ActiveLow PEG Eval : DGPU Power Enable = ActiveHigh

Primary Display

Select which of IGFX/PEG/PCI Graphics device should be Primary Display Or select HG for Hybrid Gfx.

Select PCIE Card

Select the card used on the platform Auto : Skip GPIO based Power Enable to dGPU Elk Creek 4: DGPU Power Enable = ActiveLow PEG Eval : DGPU Power Enable = ActiveHigh

HG Delay After Power Enable

Delay in milli-seconds after power enable

HG Delay After Hold Reset

Delay in milli-seconds after hold reset

Primary Display

Select which of IGFX/PEG/PCI Graphics device should be Primary Display Or select HG for Hybrid Gfx.

Internal Graphics

Keep IGFX enabled based on the setup options.

GTT Size

Select the GTT Size

Aperture Size

Select the Aperture Size Note : Above 4GB MMIO BIOS assignment is automatically enabled when selecting 2048MB aperture. To use this feature, please disable CSM Support.

PSMI SUPPORT

PSMI Enable/Disable

PSMI Region Size

Select the PSMI Region Size : Range from 32MB to 1024MB

DVMT Pre-Allocated

Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device.

DVMT Total Gfx Mem

Select DVMT5.0 Total Graphic Memory size used by the Internal Graphics Device.

DFD Restore

Select Display memory map programming for DFD Restore

Intel Graphics Pei Display Peim

Enable/Disable Pei (Early) Display

ALS Support

Valid only for ACPI. Legacy = ALS Support through the IGFX INT10 function. ACPI = ALS support through an ACPI ALS driver.

VDD Enable

Enable/Disable forcing of VDD in the BIOS

Configure GT for use

Enable/Disable GT configuration in BIOS

RC1p Support

Enable/Disable RC1p support. If RC1p is enabled, send a RC1p frequency request to PMA based other conditions being met

PAVP Enable

Enable/Disable PAVP

Cdynmax Clamping Enable

Enable/Disable Cdynmax Clamping

Cd Clock Frequency

Select the highest Cd Clock frequency supported by the platform

Cd Clock Frequency

Select the highest Cd Clock frequency supported by the platform

Cd Clock Frequency

Select the highest Cd Clock frequency supported by the platform

Skip Full CD Clock Init

Enabled: Skip Full CD clock initializaton. Disabled: Initialize the full CD clock if not initialized by Gfx PEIM

IUER Button Enable

Enable/Disable IUER Button Functionality

LCD Control

Intel(R) Ultrabook Event Support

DMI/OPI Configuration

DMI N/A

DMI Max Link Speed

Set DMI Speed Gen1/Gen2/Gen3

DMI Gen3 Eq Phase 2

Perform Gen3 Equalization Phase 2

DMI Gen3 Eq Phase 3 Method

Select Method for Gen3 Equalization Phase 3

Program Static Phase1 Eq

Program Phase1 Presets/CTLEp

Gen3 Root Port Preset value for each Lane

Gen3 Endpoint Preset value for each Lane

Gen3 Endpoint Hint value for each Lane

Gen3 RxCTLE Control

DMI De-emphasis Control

Configure the De-emphasis control on DMI

DMI Gen3 ASPM

DMI Gen3 ASPM Support. L0s is not supported for DMI Aspm for CML/TGP

DMI Gen3 ASPM

DMI Gen3 ASPM Control

DMI Gen3 ASPM Control Support. L0s is not supported for DMI Aspm for CML/TGP

DMI Gen3 L1 Exit Latency

Gen3 Root Port Preset value for each Lane

Lane 0

Value for Lane 0

Lane 1

Value for Lane 1

Lane 2

Value for Lane 2

Lane 3

Value for Lane 3

Lane 4

Value for Lane 4

Lane 5

Value for Lane 5

Lane 6

Value for Lane 6

Lane 7

Value for Lane 7

Gen3 Endpoint Preset value for each Lane

Lane 0

Value for Lane 0

Lane 1

Value for Lane 1

Lane 2

Value for Lane 2

Lane 3

Value for Lane 3

Lane 4

Value for Lane 4

Lane 5

Value for Lane 5

Lane 6

Value for Lane 6

Lane 7

Value for Lane 7

Gen3 Endpoint Hint value for each Lane

Lane 0

Value for Lane 0

Lane 1

Value for Lane 1

Lane 2

Value for Lane 2

Lane 3

Value for Lane 3

Lane 4

Value for Lane 4

Lane 5

Value for Lane 5

Lane 6

Value for Lane 6

Lane 7

Value for Lane 7

Gen3 RxCTLE Control

Bundle0

Gen3 RxCTLE setting for Bundle0 (Lane0, Lane1)

Bundle1

Gen3 RxCTLE setting for Bundle1 (Lane2, Lane3)

Bundle2

Gen3 RxCTLE setting for Bundle2 (Lane4, Lane5)

Bundle3

Gen3 RxCTLE setting for Bundle3 (Lane6, Lane7)

PEG Port Configuration

PEG 0:1:0 Not Present

Enable Root Port

Enable or Disable the Root Port

Power Down Unused Lanes

Power Down Unused Lanes. Disabled: No power saving Auto: Bios will power down unused lanes based on the max possible link width

ASPM

Control ASPM support for the PEG 0. This has no effect if PEG is not the currently active device.

OBFF

CPU PEG0 (0,1,0) OBFF Enable/Disable

LTR

CPU PEG0 (0,1,0) Latency Reporting Enable/Disable

PEG0 Hotplug

PCI Express Hot Plug Enable/Disable

Extra Bus Reserved

Extra Bus Reserved (0-7) for bridges behind this Root Bridge.

Reseved Memory

Reserved Memory for this Root Bridge (1-4096) MB

Reserved I/O

Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge.

PEG 0:1:1 Not Present

Enable Root Port

Enable or Disable the Root Port

Power Down Unused Lanes

Power Down Unused Lanes. Disabled: No power saving Auto: Bios will power down unused lanes based on the max possible link width

ASPM

Control ASPM support for the PEG 1. This has no effect if PEG is not the currently active device.

OBFF

CPU PEG1 (0,1,1) OBFF Enable/Disable

LTR

CPU PEG1 (0,1,1) Latency Reporting Enable/Disable

PEG1 Hotplug

PCI Express Hot Plug Enable/Disable

Extra Bus Reserved

Extra Bus Reserved (0-7) for bridges behind this Root Bridge.

Reseved Memory

Reserved Memory for this Root Bridge (1-4096) MB

Reserved I/O

Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge.

PEG 0:1:2 Not Present

Enable Root Port

Enable or Disable the Root Port

Power Down Unused Lanes

Power Down Unused Lanes. Disabled: No power saving Auto: Bios will power down unused lanes based on the max possible link width

ASPM

Control ASPM support for the PEG 2. This has no effect if PEG is not the currently active device.

OBFF

CPU PEG2 (0,1,2) OBFF Enable/Disable

LTR

CPU PEG2 (0,1,2) Latency Reporting Enable/Disable

PEG2 Hotplug

PCI Express Hot Plug Enable/Disable

Extra Bus Reserved

Extra Bus Reserved (0-7) for bridges behind this Root Bridge.

Reseved Memory

Reserved Memory for this Root Bridge (1-4096) MB

Reserved I/O

Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge.

PEG 0:6:0 Not Present

Enable Root Port

Enable or Disable the Root Port

Power Down Unused Lanes

Power Down Unused Lanes. Disabled: No power saving Auto: Bios will power down unused lanes based on the max possible link width

ASPM

Control ASPM support for the PEG 3. This has no effect if PEG is not the currently active device.

OBFF

CPU PEG3 (0,6,0) OBFF Enable/Disable

LTR

CPU PEG3 (0,6,0) Latency Reporting Enable/Disable

PEG2 Hotplug

PCI Express Hot Plug Enable/Disable

Extra Bus Reserved

Extra Bus Reserved (0-7) for bridges behind this Root Bridge.

Reseved Memory

Reserved Memory for this Root Bridge (1-4096) MB

Reserved I/O

Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge.

PEG0 Max Payload size

Select PEG0 Max Payload Size; Choose Auto(Default Device Capability) or force to 128/256 Bytes

PEG1 Max Payload size

Select PEG1 Max Payload Size; Choose Auto(Default Device Capability) or force to 128/256 Bytes

PEG2 Max Payload size

Select PEG2 Max Payload Size; Choose Auto(Default Device Capability) or force to 128/256 Bytes

PEG3 Max Payload size

Select PEG3 Max Payload Size; Choose Auto(Default Device Capability) or force to 128/256 Bytes

Program PCIe ASPM after OpROM

Enabled: PCIe ASPM will be programmed after OpROM. Disabled: PCIe ASPM will be programmed before OpROM.

Program Static Phase1 Eq

Program Phase1 Presets/CTLEp

Gen3 Root Port Preset value for each Lane

Gen3 Endpoint Preset value for each Lane

Gen3 Endpoint Hint value for each Lane

Gen3 Root Port Preset value for each Lane

Lane 0

Value for Lane 0

Lane 1

Value for Lane 1

Lane 2

Value for Lane 2

Lane 3

Value for Lane 3

Lane 4

Value for Lane 4

Lane 5

Value for Lane 5

Lane 6

Value for Lane 6

Lane 7

Value for Lane 7

Lane 8

Value for Lane 8

Lane 9

Value for Lane 9

Lane 10

Value for Lane 10

Lane 11

Value for Lane 11

Lane 12

Value for Lane 12

Lane 13

Value for Lane 13

Lane 14

Value for Lane 14

Lane 15

Value for Lane 15

Gen3 Endpoint Preset value for each Lane

Lane 0

Value for Lane 0

Lane 1

Value for Lane 1

Lane 2

Value for Lane 2

Lane 3

Value for Lane 3

Lane 4

Value for Lane 4

Lane 5

Value for Lane 5

Lane 6

Value for Lane 6

Lane 7

Value for Lane 7

Lane 8

Value for Lane 8

Lane 9

Value for Lane 9

Lane 10

Value for Lane 10

Lane 11

Value for Lane 11

Lane 12

Value for Lane 12

Lane 13

Value for Lane 13

Lane 14

Value for Lane 14

Lane 15

Value for Lane 15

Gen3 Endpoint Hint value for each Lane

Lane 0

Value for Lane 0

Lane 1

Value for Lane 1

Lane 2

Value for Lane 2

Lane 3

Value for Lane 3

Lane 4

Value for Lane 4

Lane 5

Value for Lane 5

Lane 6

Value for Lane 6

Lane 7

Value for Lane 7

Lane 8

Value for Lane 8

Lane 9

Value for Lane 9

Lane 10

Value for Lane 10

Lane 11

Value for Lane 11

Lane 12

Value for Lane 12

Lane 13

Value for Lane 13

Lane 14

Value for Lane 14

Lane 15

Value for Lane 15

Gen4 Root Port Preset value for each Lane

Lane 0

Value for Lane 0

Lane 1

Value for Lane 1

Lane 2

Value for Lane 2

Lane 3

Value for Lane 3

Lane 4

Value for Lane 4

Lane 5

Value for Lane 5

Lane 6

Value for Lane 6

Lane 7

Value for Lane 7

Lane 8

Value for Lane 8

Lane 9

Value for Lane 9

Lane 10

Value for Lane 10

Lane 11

Value for Lane 11

Lane 12

Value for Lane 12

Lane 13

Value for Lane 13

Lane 14

Value for Lane 14

Lane 15

Value for Lane 15

Lane 16

Value for Lane 16

Lane 17

Value for Lane 17

Lane 18

Value for Lane 18

Lane 19

Value for Lane 19

Gen4 Endpoint Preset value for each Lane

Lane 0

Value for Lane 0

Lane 1

Value for Lane 1

Lane 2

Value for Lane 2

Lane 3

Value for Lane 3

Lane 4

Value for Lane 4

Lane 5

Value for Lane 5

Lane 6

Value for Lane 6

Lane 7

Value for Lane 7

Lane 8

Value for Lane 8

Lane 9

Value for Lane 9

Lane 10

Value for Lane 10

Lane 11

Value for Lane 11

Lane 12

Value for Lane 12

Lane 13

Value for Lane 13

Lane 14

Value for Lane 14

Lane 15

Value for Lane 15

Lane 16

Value for Lane 16

Lane 17

Value for Lane 17

Lane 18

Value for Lane 18

Lane 19

Value for Lane 19

Gen4 Endpoint Hint value for each Lane

Lane 0

Value for Lane 0

Lane 1

Value for Lane 1

Lane 2

Value for Lane 2

Lane 3

Value for Lane 3

Lane 4

Value for Lane 4

Lane 5

Value for Lane 5

Lane 6

Value for Lane 6

Lane 7

Value for Lane 7

Lane 8

Value for Lane 8

Lane 9

Value for Lane 9

Lane 10

Value for Lane 10

Lane 11

Value for Lane 11

Lane 12

Value for Lane 12

Lane 13

Value for Lane 13

Lane 14

Value for Lane 14

Lane 15

Value for Lane 15

Lane 16

Value for Lane 16

Lane 17

Value for Lane 17

Lane 18

Value for Lane 18

Lane 19

Value for Lane 19

LCD Control

Primary IGFX Boot Display

Select the Video Device which will be activated during POST. This has no effect if external graphics present. Secondary boot display selection will appear based on your selection. VGA modes will be supported only on primary display

Secondary IGFX Boot Display

Select Secondary Display Device

LCD Panel Type

Select LCD panel used by Internal Graphics Device by selecting the appropriate setup item.

Panel Scaling

Select the LCD panel scaling option used by the Internal Graphics Device.

Backlight Control

Back Light Control Setting

Active LFP

Select the Active LFP Configuration. No LVDS:VBIOS does not enable LVDS. Int-LVDS:VBIOS enables LVDS driver by Integrated encoder. SDVO LVDS:VBIOS enables LVDS driver by SDVO encoder. eDP Port-A:LFP Driven by Int-DisplayPort encoder from Port-A. eDP Port-D:LFP Driven by Int-DisplayPort encoder from Port-D(through PCH).

Panel Color Depth

Select the LFP Panel Color Depth

Backlight Brightness

Set VBIOS Brightness. Range : 0-255.

Intel(R) Ultrabook Event Support

IUER Slate Enable

Enable/Disable IUER Slate Functionality

Slate Mode boot value

Choose Slate or Laptop as boot mode.

Slate Mode on S3 and S4 resume

Keep it the same as Sx entry or toggle it.

IUER Dock Enable

Enable/Disable IUER Dock Functionality

Dock Mode boot value

Choose Docked or Undocked as boot mode.

Dock Mode upon S3 and S4 resume

Keep it the same as Sx entry or toggle it.

GT - Power Management Control

RC6(Render Standby)

Check to enable render standby support.

Maximum GT frequency

Auto Updated

Disable Turbo GT frequency

Enabled: Disables Turbo GT frequency. Disabled: GT frequency is not limited

Early Command Training

SenseAmp Offset Training

Early ReadMPR Timing Centering 2D

Read MPR Training

Receive Enable Training

Jedec Write Leveling

LPDDR4 Write DQ DQS Retraining

Early Write Time Centering 2D

Early Read Time Centering 2D

Write Timing Centering 1D

Write Voltage Centering 1D

Read Timing Centering 1D

Dimm ODT Training*

Dimm On-Die Termination Training

Max RTT_WR

Caps the maximum RTT_WR in power training.

DIMM RON Training*

DIMM RON Training

Write Drive Strength/Equalization 2D*

Write Slew Rate Training*

Write Slew Rate Training

Read ODT Training*

Read On-Die Termination Training

Read Equalization Training*

Read Equalization Training

Read Amplifier Training*

Read Amplifier Training

Write Timing Centering 2D

Write Dq-Dqs Timing Centering 2D

Read Timing Centering 2D

Read Dq-Dqs Timing Centering 2D

Command Voltage Centering

Write Voltage Centering 2D

Read Voltage Centering 2D

Late Command Training

Round Trip Latency

Round Trip Latency Training

Turn Around Timing Training

Rank Margin Tool

Rank Margin Tool Training

Rank Margin Tool Per Bit

Rank Margin Tool Per Bit Training

Margin Check Limit

Checks Margin to Limit to see if next boot memory needs to be retrain

Margin Limit Check L2

L2 check threshold is scale of L1 check. Ex. 200 is 2 x L1 Check

Memory Test

Memory Test Training

DIMM SPD Alias Test

Test to determine if the SPD has been corrupted to cause memory aliasing.

Receive Enable Centering 1D

Retrain Margin Check

Write Drive Strength Up/Dn independently

Command Slew Rate Training

Command Drive Strength and Equalization

Command Normalization

Early DQ Write Drive Strength and Equalization Training

Read Voltage Centering 1D

Dimm ODT CA Training

Duty Cycle Correction

DQ DFE Training

Memory Thermal Configuration

Memory Power and Thermal Throttling

Memory Thermal Management

Enable/Disable Memory Thermal Management.

PECI Injected Temperature

Enable/Disable memory temperatures to be injected to the processor via PECI.

EXTTS# via TS-on-Board

Enable/Disable routing TS-on-Board's ALERT# and THERM# to EXTTS# pins on the PCH.

EXTTS# via TS-on-DIMM

Enable/Disable routing TS-on-DIMM's ALERT# to EXTTS# pin on the PCH.

Virtual Temperature Sensor (VTS)

Enable/Disable Virtual Temperature Sensor (VTS).

Memory Power and Thermal Throttling

DDR PowerDown and idle counter

BIOS: BIOS is in control of DDR CKE mode and idle timer value. PCODE: pcode will manage the modes.

For LPDDR Only: DDR PowerDown and idle counter

For LPDDR Only: BIOS: BIOS is in control of DDR CKE mode and idle timer value. PCODE: pcode will manage the modes.

REFRESH_2X_MODE

0- Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot

LPDDR Thermal Sensor

When enabled, MC uses MR4 to read LPDDR thermal sensors

SelfRefresh Enable

Enable, Disable(Enable= Def)

SelfRefresh IdleTimer

Self Refresh idle timer in nCK units: 0 = Auto (default), or value in range [512 .. 65535]

Throttler CKEMin Defeature

On, Off

Throttler CKEMin Timer

Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4)

For LPDDR Only: Throttler CKEMin Defeature

For LPDDR Only: On, Off

For LPDDR Only: Throttler CKEMin Timer

For LPDDR Only: Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4)

Dram Power Meter

Memory Thermal Reporting

Memory RAPL

Dram Power Meter

Use user provided power weights, scale factor, and channel power floor values

Enabled: User provided power weights, scale factor, and channel power floor values are used. Disabled: BIOS sets power weights, scale factor, and channel power floor values based on DIMMs present in system.

Energy Scale Factor

range[7;0]= [7.3;931.3]in pJ, (3= 116pJ Def)

Idle Energy Ch0Dimm0

Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)

PowerDown Energy Ch0Dimm0

PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)

Activate Energy Ch0Dimm0

Activate Energy Contribution, range[255;0],(172= Def)

Read Energy Ch0Dimm0

Read Energy Contribution, range[255;0],(212= Def)

Write Energy Ch0Dimm0

Write Energy Contribution, range[255;0],(221= Def)

Idle Energy Ch0Dimm1

Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)

PowerDown Energy Ch0Dimm1

PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)

Activate Energy Ch0Dimm1

Activate Energy Contribution, range[255;0],(172= Def)

Read Energy Ch0Dimm1

Read Energy Contribution, range[255;0],(212= Def)

Write Energy Ch0Dimm1

Write Energy Contribution, range[255;0],(221= Def)

Idle Energy Ch1Dimm0

Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)

PowerDown Energy Ch1Dimm0

PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)

Activate Energy Ch1Dimm0

Activate Energy Contribution, range[255;0],(172= Def)

Read Energy Ch1Dimm0

Read Energy Contribution, range[255;0],(212= Def)

Write Energy Ch1Dimm0

Write Energy Contribution, range[255;0],(221= Def)

Idle Energy Ch1Dimm1

Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)

PowerDown Energy Ch1Dimm1

PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)

Activate Energy Ch1Dimm1

Activate Energy Contribution, range[255;0],(172= Def)

Read Energy Ch1Dimm1

Read Energy Contribution, range[255;0],(212= Def)

Write Energy Ch1Dimm1

Write Energy Contribution, range[255;0],(221= Def)

Lock Thermal Management Registers

Enabled: lock several PCU registers related to DDR power/thermal management

Memory Thermal Reporting

Extern Therm Status

Enabled: The value from EXTTS is used Disabled: Pcode ignores the EXTTS.

Thermal Threshold Settings

Warm Threshold Ch0 Dimm0

range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM

Warm Threshold Ch0 Dimm1

range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM

Hot Threshold Ch0 Dimm0

range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM

Hot Threshold Ch0 Dimm1

range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM

Warm Threshold Ch1 Dimm0

range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM

Warm Threshold Ch1 Dimm1

range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM

Hot Threshold Ch1 Dimm0

range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM

Hot Threshold Ch1 Dimm1

range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM

Thermal Throttle Budget Settings

Warm Budget Ch0 Dimm0

range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM

Warm Budget Ch0 Dimm1

range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM

Hot Budget Ch0 Dimm0

range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM

Hot Budget Ch0 Dimm1

range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM

Warm Budget Ch1 Dimm0

range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM

Warm Budget Ch1 Dimm1

range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM

Hot Budget Ch1 Dimm0

range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM

Hot Budget Ch1 Dimm1

range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM

Memory RAPL

Rapl Power Floor Ch0

Power budget ,range[255;0], (0= 5.3W Def)

Rapl Power Floor Ch1

Power budget ,range[255;0],(0= 5.3W Def)

RAPL PL Lock

Enable= lock Rapl Limit register , Disable(Disable= Def)

RAPL PL 1 enable

Enable= enable, Disable(Disable= Def)

RAPL PL 1 Power

range[0;2^14-1]= [2047.875;0]in W, (0= Def)

RAPL PL 1 WindowX

Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def)

RAPL PL 1 WindowY

Power PL 1 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def)

RAPL PL 2 enable

Enable= enable, Disable(Disable= Def)

RAPL PL 2 Power

range[0;2^14-1]= [2047.875;0]in W, (0= Def)

RAPL PL 2 WindowX

Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def)

RAPL PL 2 WindowY

Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def)

Control Logic 1

Control Logic options

Control Logic 2

Control Logic options

Control Logic 3

Control Logic options

Control Logic 4

Control Logic options

Control Logic 5

Control Logic options

Control Logic 6

Control Logic options

Camera1

Link options

Flash Options

Camera2

Link options

Flash Options

Camera3

Link options

Flash Options

Camera4

Link options

Flash Options

Camera5

Link options

Flash Options

Camera6

Link options

Flash Options

Camera1

Sensor Model

Custom HID

Lanes Clock division

CRD Version

GPIO control

Camera position

Flash Support

Privacy LED

Rotation

PMIC Position

PMIC Position Position 1 indicates the current module is placed on the left side of the CRD-G2 card Position 2 indicates the current module is placed on the right side of the CRD-G2 card

Voltage Rail

PPR Value

PPR value of sensor

PPR Unit

PPR unit of sensor

Camera module name

MIPI port

LinkUsed

LaneUsed

MCLK

EEPROM Type

EEPROM Type 0x00: ROM_NONE 0x01: ROM_OTP 0x02: ROM_EEPROM_16K_64 0x03: ROM_EEPROM_16K_16 0x04: ROM_OTP_ACPI_ACPI 0x05: ROM_ACPI 0x06: ROM_EEPROM_BRCA016GWZ 0x07: ROM_EEPROM_24AA32 0x08: ROM_EEPROM_CAT24C08 0x09: ROM_M24C64 0x0A: ROM_DW9806B 0x10: ROM_EEPROM_CAT24C16 0x11: ROM_EEPROM_CAT24C64 0x12: ROM_EEPROM_24AA16

VCM Type

VCM Type 0x00: VCM_NONE 0x01: VCM_AD5823 0x02: VCM_DW9714 0x03: VCM_AD5816 0x04: VCM_DW9719 0x05: VCM_DW9718 0x06: VCM_DW9806B 0x07: VCM_WV517S 0x08: VCM_LC898122XA 0x09: VCM_LC898212AXB 0x0F: VCM_AK7371 0x10: VCM_BU64297GWZ

Number of I2C Components

I2C Channel

Device 0

I2C Address

Device Type

Device 1

I2C Address

Device Type

Device 2

I2C Address

Device Type

Device 3

I2C Address

Device Type

Device 4

I2C Address

Device Type

Device 5

I2C Address

Device Type

Device 6

I2C Address

Device Type

Device 7

I2C Address

Device Type

Device 8

I2C Address

Device Type

Device 9

I2C Address

Device Type

Device 10

I2C Address

Device Type

Device 11

I2C Address

Device Type

Flash Driver Selection

Select the Flash Driver as External or Internal PMIC

Camera2

Sensor Model

Custom HID

Lanes Clock division

CRD Version

GPIO control

Camera position

Flash Support

Privacy LED

Rotation

PMIC Position

PMIC Position Position 1 indicates the current module is placed on the left side of the CRD-G2 card Position 2 indicates the current module is placed on the right side of the CRD-G2 card

Voltage Rail

PPR Value

PPR value of sensor

PPR Unit

PPR unit of sensor

Camera module name

MIPI port

LinkUsed

LaneUsed

MCLK

EEPROM Type

VCM Type

Number of I2C Components

I2C Channel

Device 0

I2C Address

Device Type

Device 1

I2C Address

Device Type

Device 2

I2C Address

Device Type

Device 3

I2C Address

Device Type

Device 4

I2C Address

Device Type

Device 5

I2C Address

Device Type

Device 6

I2C Address

Device Type

Device 7

I2C Address

Device Type

Device 8

I2C Address

Device Type

Device 9

I2C Address

Device Type

Device 10

I2C Address

Device Type

Device 11

I2C Address

Device Type

Flash Driver Selection

Select the Flash Driver as External or Internal PMIC

Camera3

Sensor Model

Custom HID

Lanes Clock division

CRD Version

GPIO control

Camera position

Flash Support

Privacy LED

Rotation

PMIC Position

PMIC Position Position 1 indicates the current module is placed on the left side of the CRD-G2 card Position 2 indicates the current module is placed on the right side of the CRD-G2 card

Voltage Rail

PPR Value

PPR value of sensor

PPR Unit

PPR unit of sensor

Camera module name

MIPI port

LinkUsed

LaneUsed

MCLK

EEPROM Type

VCM Type

Number of I2C Components

I2C Channel

Device 0

I2C Address

Device Type

Device 1

I2C Address

Device Type

Device 2

I2C Address

Device Type

Device 3

I2C Address

Device Type

Device 4

I2C Address

Device Type

Device 5

I2C Address

Device Type

Device 6

I2C Address

Device Type

Device 7

I2C Address

Device Type

Device 8

I2C Address

Device Type

Device 9

I2C Address

Device Type

Device 10

I2C Address

Device Type

Device 11

I2C Address

Device Type

Flash Driver Selection

Select the Flash Driver as External or Internal PMIC

Camera4

Sensor Model

Custom HID

Lanes Clock division

CRD Version

GPIO control

Camera position

Flash Support

Privacy LED

Rotation

PMIC Position

PMIC Position Position 1 indicates the current module is placed on the left side of the CRD-G2 card Position 2 indicates the current module is placed on the right side of the CRD-G2 card

Voltage Rail

PPR Value

PPR value of sensor

PPR Unit

PPR unit of sensor

Camera module name

MIPI port

LinkUsed

LaneUsed

MCLK

EEPROM Type

VCM Type

Number of I2C Components

I2C Channel

Device 0

I2C Address

Device Type

Device 1

I2C Address

Device Type

Device 2

I2C Address

Device Type

Device 3

I2C Address

Device Type

Device 4

I2C Address

Device Type

Device 5

I2C Address

Device Type

Device 6

I2C Address

Device Type

Device 7

I2C Address

Device Type

Device 8

I2C Address

Device Type

Device 9

I2C Address

Device Type

Device 10

I2C Address

Device Type

Device 11

I2C Address

Device Type

Flash Driver Selection

Select the Flash Driver as External or Internal PMIC

Camera5

Sensor Model

Custom HID

Lanes Clock division

CRD Version

GPIO control

Camera position

Flash Support

Privacy LED

Rotation

PMIC Position

PMIC Position Position 1 indicates the current module is placed on the left side of the CRD-G2 card Position 2 indicates the current module is placed on the right side of the CRD-G2 card

Voltage Rail

PPR Value

PPR value of sensor

PPR Unit

PPR unit of sensor

Camera module name

MIPI port

LinkUsed

LaneUsed

MCLK

EEPROM Type

VCM Type

Number of I2C Components

I2C Channel

Device 0

I2C Address

Device Type

Device 1

I2C Address

Device Type

Device 2

I2C Address

Device Type

Device 3

I2C Address

Device Type

Device 4

I2C Address

Device Type

Device 5

I2C Address

Device Type

Device 6

I2C Address

Device Type

Device 7

I2C Address

Device Type

Device 8

I2C Address

Device Type

Device 9

I2C Address

Device Type

Device 10

I2C Address

Device Type

Device 11

I2C Address

Device Type

Flash Driver Selection

Select the Flash Driver as External or Internal PMIC

Camera6

Sensor Model

Custom HID

Lanes Clock division

CRD Version

GPIO control

Camera position

Flash Support

Privacy LED

Rotation

PMIC Position

PMIC Position Position 1 indicates the current module is placed on the left side of the CRD-G2 card Position 2 indicates the current module is placed on the right side of the CRD-G2 card

Voltage Rail

PPR Value

PPR value of sensor

PPR Unit

PPR unit of sensor

Camera module name

MIPI port

LinkUsed

LaneUsed

MCLK

EEPROM Type

VCM Type

Number of I2C Components

I2C Channel

Device 0

I2C Address

Device Type

Device 1

I2C Address

Device Type

Device 2

I2C Address

Device Type

Device 3

I2C Address

Device Type

Device 4

I2C Address

Device Type

Device 5

I2C Address

Device Type

Device 6

I2C Address

Device Type

Device 7

I2C Address

Device Type

Device 8

I2C Address

Device Type

Device 9

I2C Address

Device Type

Device 10

I2C Address

Device Type

Device 11

I2C Address

Device Type

Flash Driver Selection

Select the Flash Driver as External or Internal PMIC

Control Logic options

Control Logic Type

CRD Version

Input Clock

PCH Clock Source

This option specifies which IMGCLKOUT is chosen

PMIC Flash Panel

I2C Channel

I2C Address

WLED1 Type

WLED Type

WLED1 Flash Max Current

WLED Flash Max Current Valid range is 0x00-0x1F 0x00 for HW default max current

WLED1 Torch Max Current

WLED Torch Max Current Valid range is 0x00-0x07 0x00 for HW default max current

WLED2 Type

WLED Type

WLED2 Flash Max Current

WLED Flash Max Current Valid range is 0x00-0x1F 0x00 for HW default max current

WLED2 Torch Max Current

WLED Torch Max Current Valid range is 0x00-0x07 0x00 for HW default max current

SubPlatformId

Number of GPIO Pins

GPIO 0

Group Pad Number

Group Number

Function

Active Value

Initial Value

GPIO 1

Group Pad Number

Group Number

Function

Active Value

Initial Value

GPIO 2

Group Pad Number

Group Number

Function

Active Value

Initial Value

GPIO 3

Group Pad Number

Group Number

Function

Active Value

Initial Value

Control Logic options

Control Logic Type

CRD Version

Input Clock

PCH Clock Source

This option specifies which IMGCLKOUT is chosen

PMIC Flash Panel

I2C Channel

I2C Address

WLED1 Type

WLED Type

WLED1 Flash Max Current

WLED Flash Max Current Valid range is 0x00-0x1F 0x00 for HW default max current

WLED1 Torch Max Current

WLED Torch Max Current Valid range is 0x00-0x07 0x00 for HW default max current

WLED2 Type

WLED Type

WLED2 Flash Max Current

WLED Flash Max Current Valid range is 0x00-0x1F 0x00 for HW default max current

WLED2 Torch Max Current

WLED Torch Max Current Valid range is 0x00-0x07 0x00 for HW default max current

SubPlatformId

Number of GPIO Pins

GPIO 0

Group Pad Number

Group Number

Function

Active Value

Initial Value

GPIO 1

Group Pad Number

Group Number

Function

Active Value

Initial Value

GPIO 2

Group Pad Number

Group Number

Function

Active Value

Initial Value

GPIO 3

Group Pad Number

Group Number

Function

Active Value

Initial Value

Control Logic options

Control Logic Type

CRD Version

Input Clock

PCH Clock Source

This option specifies which IMGCLKOUT is chosen

PMIC Flash Panel

I2C Channel

I2C Address

WLED1 Type

WLED Type

WLED1 Flash Max Current

WLED Flash Max Current Valid range is 0x00-0x1F 0x00 for HW default max current

WLED1 Torch Max Current

WLED Torch Max Current Valid range is 0x00-0x07 0x00 for HW default max current

WLED2 Type

WLED Type

WLED2 Flash Max Current

WLED Flash Max Current Valid range is 0x00-0x1F 0x00 for HW default max current

WLED2 Torch Max Current

WLED Torch Max Current Valid range is 0x00-0x07 0x00 for HW default max current

SubPlatformId

Number of GPIO Pins

GPIO 0

Group Pad Number

Group Number

Function

Active Value

Initial Value

GPIO 1

Group Pad Number

Group Number

Function

Active Value

Initial Value

GPIO 2

Group Pad Number

Group Number

Function

Active Value

Initial Value

GPIO 3

Group Pad Number

Group Number

Function

Active Value

Initial Value

Control Logic options

Control Logic Type

CRD Version

Input Clock

PCH Clock Source

This option specifies which IMGCLKOUT is chosen

PMIC Flash Panel

I2C Channel

I2C Address

WLED1 Type

WLED Type

WLED1 Flash Max Current

WLED Flash Max Current Valid range is 0x00-0x1F 0x00 for HW default max current

WLED1 Torch Max Current

WLED Torch Max Current Valid range is 0x00-0x07 0x00 for HW default max current

WLED2 Type

WLED Type

WLED2 Flash Max Current

WLED Flash Max Current Valid range is 0x00-0x1F 0x00 for HW default max current

WLED2 Torch Max Current

WLED Torch Max Current Valid range is 0x00-0x07 0x00 for HW default max current

SubPlatformId

Number of GPIO Pins

GPIO 0

Group Pad Number

Group Number

Function

Active Value

Initial Value

GPIO 1

Group Pad Number

Group Number

Function

Active Value

Initial Value

GPIO 2

Group Pad Number

Group Number

Function

Active Value

Initial Value

GPIO 3

Group Pad Number

Group Number

Function

Active Value

Initial Value

Control Logic options

Control Logic Type

CRD Version

Input Clock

PCH Clock Source

This option specifies which IMGCLKOUT is chosen

PMIC Flash Panel

I2C Channel

I2C Address

WLED1 Type

WLED Type

WLED1 Flash Max Current

WLED Flash Max Current Valid range is 0x00-0x1F 0x00 for HW default max current

WLED1 Torch Max Current

WLED Torch Max Current Valid range is 0x00-0x07 0x00 for HW default max current

WLED2 Type

WLED Type

WLED2 Flash Max Current

WLED Flash Max Current Valid range is 0x00-0x1F 0x00 for HW default max current

WLED2 Torch Max Current

WLED Torch Max Current Valid range is 0x00-0x07 0x00 for HW default max current

SubPlatformId

Number of GPIO Pins

GPIO 0

Group Pad Number

Group Number

Function

Active Value

Initial Value

GPIO 1

Group Pad Number

Group Number

Function

Active Value

Initial Value

GPIO 2

Group Pad Number

Group Number

Function

Active Value

Initial Value

GPIO 3

Group Pad Number

Group Number

Function

Active Value

Initial Value

Control Logic options

Control Logic Type

CRD Version

Input Clock

PCH Clock Source

This option specifies which IMGCLKOUT is chosen

PMIC Flash Panel

I2C Channel

I2C Address

WLED1 Type

WLED Type

WLED1 Flash Max Current

WLED Flash Max Current Valid range is 0x00-0x1F 0x00 for HW default max current

WLED1 Torch Max Current

WLED Torch Max Current Valid range is 0x00-0x07 0x00 for HW default max current

WLED2 Type

WLED Type

WLED2 Flash Max Current

WLED Flash Max Current Valid range is 0x00-0x1F 0x00 for HW default max current

WLED2 Torch Max Current

WLED Torch Max Current Valid range is 0x00-0x07 0x00 for HW default max current

SubPlatformId

Number of GPIO Pins

GPIO 0

Group Pad Number

Group Number

Function

Active Value

Initial Value

GPIO 1

Group Pad Number

Group Number

Function

Active Value

Initial Value

GPIO 2

Group Pad Number

Group Number

Function

Active Value

Initial Value

GPIO 3

Group Pad Number

Group Number

Function

Active Value

Initial Value

Flash1

Flash Model

Camera module name

I2C Channel

I2C Address

Flash Trigger Gpio

Group Pad Number

Group Number

Active Value

Initial Value

Flash Driver Operating Mode

Select the Flash Driver Operating Mode as Disabled , Torch or Flash

Flash2

Flash Model

Camera module name

I2C Channel

I2C Address

Flash Trigger Gpio

Group Pad Number

Group Number

Active Value

Initial Value

Flash Driver Operating Mode

Select the Flash Driver Operating Mode as Disabled , Torch or Flash

Flash3

Flash Model

Camera module name

I2C Channel

I2C Address

Flash Trigger Gpio

Group Pad Number

Group Number

Active Value

Initial Value

Flash Driver Operating Mode

Select the Flash Driver Operating Mode as Disabled , Torch or Flash

Flash4

Flash Model

Camera module name

I2C Channel

I2C Address

Flash Trigger Gpio

Group Pad Number

Group Number

Active Value

Initial Value

Flash Driver Operating Mode

Select the Flash Driver Operating Mode as Disabled , Torch or Flash

Flash5

Flash Model

Camera module name

I2C Channel

I2C Address

Flash Trigger Gpio

Group Pad Number

Group Number

Active Value

Initial Value

Flash Driver Operating Mode

Select the Flash Driver Operating Mode as Disabled , Torch or Flash

Flash6

Flash Model

Camera module name

I2C Channel

I2C Address

Flash Trigger Gpio

Group Pad Number

Group Number

Active Value

Initial Value

Flash Driver Operating Mode

Select the Flash Driver Operating Mode as Disabled , Torch or Flash

VMD Configuration

Enable VMD controller

Enable/Disable to VMD controller

Enable VMD portA Support

Enable/Disable to VMD portA support

RP-A BDF details N/A

Enable VMD portB Support

Enable/Disable to VMD portB support

RP-B BDF details N/A

Enable VMD portC Support

Enable/Disable to VMD portC support

RP-C BDF details N/A

Enable VMD portD Support

Enable/Disable to VMD portD support

RP-D BDF details N/A

VMD Config Bar Size

Set The VMD Config Bar Size

VMD Config Bar Attributes

Set The VMD Config Bar Attributes

VMD Mem Bar1 Size

Set The VMD Mem Bar1 Size

VMD Mem Bar1 Attributes

Set The VMD Mem Bar1 Attributes

VMD Mem Bar2 Size

Set The VMD Mem Bar2 Size

VMD Mem Bar2 Attributes

Set The VMD Mem Bar2 Attributes

RAID0

Enable/Disable RAID0 support

RAID1

Enable/Disable RAID1 support

RAID5

Enable/Disable RAID5 support

RAID10

Enable/Disable RAID10 support

Intel Rapid Recovery Technology

Enable/Disable Intel Rapid Recovery Technology.

RRT volumes can span internal and eSATA drives

Enable/Disable RRT volumes can span internal and eSATA drives.

Intel(R) Optane(TM) Memory

Enable/Disable System Acceleration with Intel(R) Optane(TM) Memory feature.

Display Configuration

PCI Express Configuration

PCI Express Clock Gating

PCI Express Clock Gating Enable/Disable for each root port.

Fia Programming

Load Fia Configuration if Enabled for each root port.

PCI Express Power Gating

PCI Express Power Gating Enable/Disable for each root port.

Compliance Test Mode

Enable when using Compliance Load Board

PCIe function swap

When Disabled, prevents PCIE rootport function swap. If any function other than 0th is enabled, 0th will become visible.

Assertion on Link Down GPIOs

GPIO Assertion on Link Down

Enable ClockReq Messaging

Enable or Disable ClockReq Messaging

PCI Express Slot Selection

Select the PCIe M2 or CEMx4 slot

PCI Express Root Port 1

PCI Express Root Port 1 Not present in this SKU

PCI Express Root Port 2

PCI Express Root Port 2 Not present in this SKU

PCI Express Root Port 3

PCI Express Root Port 3 Not present in this SKU

PCI Express Root Port 4

PCI Express Root Port 4 Not present in this SKU

PCIE1 Cm

PCIE1 Cp

PCIE2 Cm

PCIE2 Cp

PCIE3 Cm

PCIE3 Cp

PCIE4 Cm

PCIE4 Cp

PCIE5 Cm

PCIE5 Cp

PCIE6 Cm

PCIE6 Cp

PCIE7 Cm

PCIE7 Cp

PCIE8 Cm

PCIE8 Cp

PCIE9 Cm

PCIE9 Cp

PCIE10 Cm

PCIE10 Cp

PCIE11 Cm

PCIE11 Cp

PCIE12 Cm

PCIE12 Cp

PCIE13 Cm

PCIE13 Cp

PCIE14 Cm

PCIE14 Cp

PCIE15 Cm

PCIE15 Cp

PCIE16 Cm

PCIE16 Cp

PCIE17 Cm

PCIE17 Cp

PCIE18 Cm

PCIE18 Cp

PCIE19 Cm

PCIE19 Cp

PCIE20 Cm

PCIE29 Cp

PCI Express Root Port 1

Control the PCI Express Root Port.

Connection Type

Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.

ASPM

PCI Express Active State Power Management settings.

L1 Substates

PCI Express L1 Substates settings.L1SS cannot be enabled when CLKREQMSG is disabled

Gen3 Eq Phase3 Method

PCIe Gen3 Equalization Phase 3 Method

Gen4 Eq Phase3 Method

PCIe Gen3 Equalization Phase 3 Method

ACS

Enable/Disable Access Control Services Extended Capability

PTM

Enable/Disable Precision Time Measurement

DPC

Enable/Disable Downstream Port Containment

FOM Scoreboard Control Policy

Select the FOM Scoreboard Control Policy, when set to Auto, speed is based on TLS

Enable/Disable Virtual Channel

Multi-VC

Enable/Disable Multi Virtual Channel

EDPC

Enable/Disable Rootport extensions for Downstream Port Containment

URR

PCI Express Unsupported Request Reporting Enable/Disable.

FER

PCI Express Device Fatal Error Reporting Enable/Disable.

NFER

PCI Express Device Non-Fatal Error Reporting Enable/Disable.

CER

PCI Express Device Correctable Error Reporting Enable/Disable.

CTO

PCI Express Completion Timer TO Enable/Disable.

SEFE

Root PCI Express System Error on Fatal Error Enable/Disable.

SENFE

Root PCI Express System Error on Non-Fatal Error Enable/Disable.

SECE

Root PCI Express System Error on Correctable Error Enable/Disable.

PME SCI

PCI Express PME SCI Enable/Disable.

Hot Plug

PCI Express Hot Plug Enable/Disable.

Advanced Error Reporting

Advanced Error Reporting Enable/Disable.

PCIe Speed

Configure PCIe Speed

Transmitter Half Swing

Transmitter Half Swing Enable/Disable.

Detect Timeout

The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.

P2P Support

Program P2P Support Registers according to setup option

SA PCIe LTR Configuration

LTR

SA PCIE Latency Reporting Enable/Disable

Snoop Latency Override

Snoop Latency Override for SA PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Snoop Latency Value

LTR Snoop Latency value of SA PCIE

Snoop Latency Multiplier

LTR Snoop Latency Multiplier of SA PCIE

Non Snoop Latency Override

Non Snoop Latency Override for SA PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Non Snoop Latency Value

LTR Non Snoop Latency value of PCH PCIE

Non Snoop Latency Multiplier

LTR Non Snoop Latency Multiplier of SA PCIE

Force LTR Override

Force LTR Override for SA PCIE. Disabled: LTR override values will not be forced. Enable: LTR override values will be forced and LTR messages from the device will be ignored.

LTR Lock

PCIE LTR Configuration Lock

CPU PCIe Gen3 HWEQ Config

UPTP

Upstream Port Transmitter Preset

DPTP

Downstream Port Transmitter Preset

CPU PCIe Gen4 HWEQ Config

UPTP

Upstream Port Transmitter Preset

DPTP

Downstream Port Transmitter Preset

PCI Express Gen3 Eq Lanes

PCIE1 Cm

PCIE1 Cp

PCIE2 Cm

PCIE2 Cp

PCIE3 Cm

PCIE3 Cp

PCIE4 Cm

PCIE4 Cp

PCI Express Root Port 2

Control the PCI Express Root Port.

Connection Type

Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.

ASPM

PCI Express Active State Power Management settings.

L1 Substates

PCI Express L1 Substates settings.L1SS cannot be enabled when CLKREQMSG is disabled

Gen3 Eq Phase3 Method

PCIe Gen3 Equalization Phase 3 Method

Gen4 Eq Phase3 Method

PCIe Gen3 Equalization Phase 3 Method

ACS

Enable/Disable Access Control Services Extended Capability

PTM

Enable/Disable Precision Time Measurement

DPC

Enable/Disable Downstream Port Containment

FOM Scoreboard Control Policy

Select the FOM Scoreboard Control Policy, when set to Auto, speed is based on TLS

Enable/Disable Virtual Channel

Multi-VC

Enable/Disable Multi Virtual Channel

EDPC

Enable/Disable Rootport extensions for Downstream Port Containment

URR

PCI Express Unsupported Request Reporting Enable/Disable.

FER

PCI Express Device Fatal Error Reporting Enable/Disable.

NFER

PCI Express Device Non-Fatal Error Reporting Enable/Disable.

CER

PCI Express Device Correctable Error Reporting Enable/Disable.

CTO

PCI Express Completion Timer TO Enable/Disable.

SEFE

Root PCI Express System Error on Fatal Error Enable/Disable.

SENFE

Root PCI Express System Error on Non-Fatal Error Enable/Disable.

SECE

Root PCI Express System Error on Correctable Error Enable/Disable.

PME SCI

PCI Express PME SCI Enable/Disable.

Hot Plug

PCI Express Hot Plug Enable/Disable.

Advanced Error Reporting

Advanced Error Reporting Enable/Disable.

PCIe Speed

Configure PCIe Speed

Transmitter Half Swing

Transmitter Half Swing Enable/Disable.

Detect Timeout

The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.

P2P Support

Program P2P Support Registers according to setup option

SA PCIe LTR Configuration

LTR

SA PCIE Latency Reporting Enable/Disable

Snoop Latency Override

Snoop Latency Override for SA PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Snoop Latency Value

LTR Snoop Latency value of SA PCIE

Snoop Latency Multiplier

LTR Snoop Latency Multiplier of SA PCIE

Non Snoop Latency Override

Non Snoop Latency Override for SA PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Non Snoop Latency Value

LTR Non Snoop Latency value of PCH PCIE

Non Snoop Latency Multiplier

LTR Non Snoop Latency Multiplier of SA PCIE

Force LTR Override

Force LTR Override for SA PCIE. Disabled: LTR override values will not be forced. Enable: LTR override values will be forced and LTR messages from the device will be ignored.

LTR Lock

PCIE LTR Configuration Lock

CPU PCIe Gen3 HWEQ Config

UPTP

Upstream Port Transmitter Preset

DPTP

Downstream Port Transmitter Preset

CPU PCIe Gen4 HWEQ Config

UPTP

Upstream Port Transmitter Preset

DPTP

Downstream Port Transmitter Preset

PCI Express Gen3 Eq Lanes

PCIE1 Cm

PCIE1 Cp

PCIE2 Cm

PCIE2 Cp

PCIE3 Cm

PCIE3 Cp

PCIE4 Cm

PCIE4 Cp

PCI Express Root Port 3

Control the PCI Express Root Port.

Connection Type

Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.

ASPM

PCI Express Active State Power Management settings.

L1 Substates

PCI Express L1 Substates settings.L1SS cannot be enabled when CLKREQMSG is disabled

Gen3 Eq Phase3 Method

PCIe Gen3 Equalization Phase 3 Method

Gen4 Eq Phase3 Method

PCIe Gen3 Equalization Phase 3 Method

ACS

Enable/Disable Access Control Services Extended Capability

PTM

Enable/Disable Precision Time Measurement

DPC

Enable/Disable Downstream Port Containment

FOM Scoreboard Control Policy

Select the FOM Scoreboard Control Policy, when set to Auto, speed is based on TLS

Enable/Disable Virtual Channel

Multi-VC

Enable/Disable Multi Virtual Channel

EDPC

Enable/Disable Rootport extensions for Downstream Port Containment

URR

PCI Express Unsupported Request Reporting Enable/Disable.

FER

PCI Express Device Fatal Error Reporting Enable/Disable.

NFER

PCI Express Device Non-Fatal Error Reporting Enable/Disable.

CER

PCI Express Device Correctable Error Reporting Enable/Disable.

CTO

PCI Express Completion Timer TO Enable/Disable.

SEFE

Root PCI Express System Error on Fatal Error Enable/Disable.

SENFE

Root PCI Express System Error on Non-Fatal Error Enable/Disable.

SECE

Root PCI Express System Error on Correctable Error Enable/Disable.

PME SCI

PCI Express PME SCI Enable/Disable.

Hot Plug

PCI Express Hot Plug Enable/Disable.

Advanced Error Reporting

Advanced Error Reporting Enable/Disable.

PCIe Speed

Configure PCIe Speed

Transmitter Half Swing

Transmitter Half Swing Enable/Disable.

Detect Timeout

The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.

P2P Support

Program P2P Support Registers according to setup option

SA PCIe LTR Configuration

LTR

SA PCIE Latency Reporting Enable/Disable

Snoop Latency Override

Snoop Latency Override for SA PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Snoop Latency Value

LTR Snoop Latency value of SA PCIE

Snoop Latency Multiplier

LTR Snoop Latency Multiplier of SA PCIE

Non Snoop Latency Override

Non Snoop Latency Override for SA PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Non Snoop Latency Value

LTR Non Snoop Latency value of PCH PCIE

Non Snoop Latency Multiplier

LTR Non Snoop Latency Multiplier of SA PCIE

Force LTR Override

Force LTR Override for SA PCIE. Disabled: LTR override values will not be forced. Enable: LTR override values will be forced and LTR messages from the device will be ignored.

LTR Lock

PCIE LTR Configuration Lock

CPU PCIe Gen3 HWEQ Config

UPTP

Upstream Port Transmitter Preset

DPTP

Downstream Port Transmitter Preset

CPU PCIe Gen4 HWEQ Config

UPTP

Upstream Port Transmitter Preset

DPTP

Downstream Port Transmitter Preset

PCI Express Gen3 Eq Lanes

PCIE1 Cm

PCIE1 Cp

PCIE2 Cm

PCIE2 Cp

PCIE3 Cm

PCIE3 Cp

PCIE4 Cm

PCIE4 Cp

PCI Express Root Port 4

Control the PCI Express Root Port.

Connection Type

Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.

ASPM

PCI Express Active State Power Management settings.

L1 Substates

PCI Express L1 Substates settings.L1SS cannot be enabled when CLKREQMSG is disabled

Gen3 Eq Phase3 Method

PCIe Gen3 Equalization Phase 3 Method

Gen4 Eq Phase3 Method

PCIe Gen3 Equalization Phase 3 Method

ACS

Enable/Disable Access Control Services Extended Capability

PTM

Enable/Disable Precision Time Measurement

DPC

Enable/Disable Downstream Port Containment

FOM Scoreboard Control Policy

Select the FOM Scoreboard Control Policy, when set to Auto, speed is based on TLS

Enable/Disable Virtual Channel

Multi-VC

Enable/Disable Multi Virtual Channel

EDPC

Enable/Disable Rootport extensions for Downstream Port Containment

URR

PCI Express Unsupported Request Reporting Enable/Disable.

FER

PCI Express Device Fatal Error Reporting Enable/Disable.

NFER

PCI Express Device Non-Fatal Error Reporting Enable/Disable.

CER

PCI Express Device Correctable Error Reporting Enable/Disable.

CTO

PCI Express Completion Timer TO Enable/Disable.

SEFE

Root PCI Express System Error on Fatal Error Enable/Disable.

SENFE

Root PCI Express System Error on Non-Fatal Error Enable/Disable.

SECE

Root PCI Express System Error on Correctable Error Enable/Disable.

PME SCI

PCI Express PME SCI Enable/Disable.

Hot Plug

PCI Express Hot Plug Enable/Disable.

Advanced Error Reporting

Advanced Error Reporting Enable/Disable.

PCIe Speed

Configure PCIe Speed

Transmitter Half Swing

Transmitter Half Swing Enable/Disable.

Detect Timeout

The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.

P2P Support

Program P2P Support Registers according to setup option

SA PCIe LTR Configuration

LTR

SA PCIE Latency Reporting Enable/Disable

Snoop Latency Override

Snoop Latency Override for SA PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Snoop Latency Value

LTR Snoop Latency value of SA PCIE

Snoop Latency Multiplier

LTR Snoop Latency Multiplier of SA PCIE

Non Snoop Latency Override

Non Snoop Latency Override for SA PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Non Snoop Latency Value

LTR Non Snoop Latency value of PCH PCIE

Non Snoop Latency Multiplier

LTR Non Snoop Latency Multiplier of SA PCIE

Force LTR Override

Force LTR Override for SA PCIE. Disabled: LTR override values will not be forced. Enable: LTR override values will be forced and LTR messages from the device will be ignored.

LTR Lock

PCIE LTR Configuration Lock

CPU PCIe Gen3 HWEQ Config

UPTP

Upstream Port Transmitter Preset

DPTP

Downstream Port Transmitter Preset

CPU PCIe Gen4 HWEQ Config

UPTP

Upstream Port Transmitter Preset

DPTP

Downstream Port Transmitter Preset

PCI Express Gen3 Eq Lanes

PCIE1 Cm

PCIE1 Cp

PCIE2 Cm

PCIE2 Cp

PCIE3 Cm

PCIE3 Cp

PCIE4 Cm

PCIE4 Cp

PCIE Configuration

IMR Configuration

PCIe IMR

Enable/Disable PCIe IMR

PCIe IMR Size

PCIe Reserved Memory Size to be requested in MB. Maximum value of 1024 MB

PCIe RP Location for IMR

Select SA or PCH roor port associated with IMR

RP index for IMR

Selects which root port will be associated with IMR

RP index for IMR

Selects which root port will be associated with IMR

PCH-IO Configuration

PCI Express Configuration

SATA And RST Configuration

USB Configuration

Security Configuration

HD Audio Configuration

THC Configuration

SerialIo Configuration

ISH Configuration

Pch Thermal Throttling Control

FIVR Configuration

PCH LAN Controller

Enable/Disable onboard NIC.

LAN Wake From DeepSx

Wake from DeepSx by the assertion of LAN_WAKE# pin

Wake on LAN Enable

Enable/Disable integrated LAN to wake the system.

SLP_LAN# Low on DC Power

Enable/Disable SLP_LAN# Low on DC Power.

PCH LAN Controller No GbE Region

EFI Network

Enable/Disable EFI Network support for onboard LAN or WiFi module.

Sensor Hub Type

Choose the Sensor Hub Type, 'None' will Suppress 'I2C Sensor Hub' Setup Option','I2C' Will Suppress 'ALS' Setup Option and 'USB' will Suppress Both I2C and ALS.

DeepSx Power Policies

configure the DeepSx Mode configuration.

PS_ON Enable

Enable or disable PS_ON ()support a new C10 state from the CPU on desktop SKUs that enables a lower power target that will be required by the California Energy Commission (CEC).

Wake on WLAN and BT Enable

Enable/Disable PCI Express Wireless LAN and Bluetooth to wake the system.

DeepSx Wake on WLAN and BT Enable

Enable/Disable PCI Express Wireless LAN and Bluetooth to wake the system from DeepSx.

Disable DSX ACPRESENT PullDown

Disable PCH internal ACPRESENT PullDown when DeepSx or G3 exit.

High Precision Timer

Enable or Disable the High Precision Event Timer.

State After G3

Specify what state to go to when power is re-applied after a power failure (G3 state).

Port 80h Redirection

Control where the Port 80h cycles are sent.

Enhance Port 80h LPC Decoding

Support the word/dword decoding of port 80h behind LPC

Compatible Revision ID

Enable/Disable the PCH Compatible Revision ID feature

Legacy IO Low Latency

Set to enable low latency of legacy IO. Some systems require lower IO latency irrespective of power. This is a tradeoff between power and IO latency.

PCH Cross Throttling

Enable/Disable the PCH Cross Throttling feature. Only ULT support this feature.

PCH Energy Reporting

Enable Energy Report. MUST set it as ENABLED. This is only for test purpose.

LPM S0i2.0

Enable/Disable S0ix sub-state. This setting is for test purpose. S0ix sub-states should be enabled for production.

LPM S0i2.1

Enable/Disable S0ix sub-state. This setting is for test purpose. S0ix sub-states should be enabled for production.

LPM S0i2.2

Enable/Disable S0ix sub-state. This setting is for test purpose. S0ix sub-states should be enabled for production.

LPM S0i3.0

Enable/Disable S0ix sub-state. This setting is for test purpose. S0ix sub-states should be enabled for production.

LPM S0i3.1

Enable/Disable S0ix sub-state. This setting is for test purpose. S0ix sub-states should be enabled for production.

LPM S0i3.2

Enable/Disable S0ix sub-state. This setting is for test purpose. S0ix sub-states should be enabled for production.

LPM S0i3.3

Enable/Disable S0ix sub-state. This setting is for test purpose. S0ix sub-states should be enabled for production.

LPM S0i3.4

Enable/Disable S0ix sub-state. This setting is for test purpose. S0ix sub-states should be enabled for production.

IEH Mode

Enable/Bypass IEH Mode

Enable TCO Timer

Enable/Disable TCO timer. When disabled, it disables PCH ACPI timer, stops TCO timer, and ACPI WDAT table will not be published.

Pcie Pll SSC

Pcie Pll SSC percentage.AUTO - Keep hw default, no BIOS override. Range is 0.0%-2.0%.

IOTG PLL SSCEN (CPU Side SSC)

Enable/Disable IOTG PLL SSCEN

IOAPIC 24-119 Entries

Enables/Disables IOAPIC 24-119 Entries. IRQ24-119 may be used by PCH devices. Disabling those interrupts may cause certain devices failure.

Enable 8254 Clock Gate

Enables/Disables 8254 clock gate in early phase. Set 8254CGE is necessary for SLP_S0 support. Platform is albe to disable this policy and set 8254CGE in late phase.

Lock PCH Sideband Access

Lock PCH Sideband access, include SideBand interface lock and SideBand PortID mask for certain end point (e.g. PSFx). The option is invalid if POSTBOOT SAI is set.

Flash Protection Range Registers (FPRR)

Enable Flash Protection Range Registers

SPD Write Disable

Enable/Disable setting SPD Write Disable. For security recommendations, SPD write disable bit must be set.

LGMR

64KB memory block for LGMR (LPC Memory Range Decode)

HOST_C10 reporting to Slave

This option enables HOST_C10 reporting to Slave via eSPI Virtual Wire

OS IDLE Mode

Enable/Disable OS Idle Mode Feature

S0ix Auto Demotion

Enable/Disable Host Low Power Mode S0ix Auto-Demotion

Latch Events C10 Exit

Enable/Disable Latch Events on C10 Exit

Hybrid Storage Detection and Configuration Mode

Select Hybrid Storage Detection and Configuration Mode

Extended BIOS Range Decode

Enabling this will make memory cycles falling in a specific area to be redirected to SPI flash controller

PCI Express Configuration

DMI Link ASPM Control

The control of Active State Power Management of the DMI Link.

Port8xh Decode

PCI Express Port8xh Decode Enable/Disable.

Port8xh Decode Port#

Select PCI Express Port8xh Decode Root Port. User to ensure port availability

Peer Memory Write Enable

Peer Memory Write Enable/Disable

Compliance Test Mode

Enable when using Compliance Load Board

PCIe function swap

When Disabled, prevents PCIE rootport function swap. If any function other than 0th is enabled, 0th will become visible.

PCIe EQ settings

PCI Express Root Port 1

PCI Express Root Port 1 Not present in this SKU

PCI Express Root Port 1 Shadowed by x2/x4 port

PCI Express Root Port 1 Lane configured as USB/SATA/UFS/GbE

PCI Express Root Port 2

PCI Express Root Port 2 Not present in this SKU

PCI Express Root Port 2 Shadowed by x2/x4 port

PCI Express Root Port 2 Lane configured as USB/SATA/UFS/GbE

PCI Express Root Port 3

PCI Express Root Port 3 Not present in this SKU

PCI Express Root Port 3 Shadowed by x2/x4 port

PCI Express Root Port 3 Lane configured as USB/SATA/UFS/GbE

PCI Express Root Port 4

PCI Express Root Port 4 Not present in this SKU

PCI Express Root Port 4 Shadowed by x2/x4 port

PCI Express Root Port 4 Lane configured as USB/SATA/UFS/GbE

PCI Express Root Port 5

PCI Express Root Port 5 Not present in this SKU

PCI Express Root Port 5 Shadowed by x2/x4 port

PCI Express Root Port 5 Lane configured as USB/SATA/UFS/GbE

PCI Express Root Port 6

PCI Express Root Port 6 Not present in this SKU

PCI Express Root Port 6 Shadowed by x2/x4 port

PCI Express Root Port 6 Lane configured as USB/SATA/UFS/GbE

PCI Express Root Port 7

PCI Express Root Port 7 Not present in this SKU

PCI Express Root Port 7 Shadowed by x2/x4 port

PCI Express Root Port 7 Lane configured as USB/SATA/UFS/GbE

PCI Express Root Port 8

PCI Express Root Port 8 Not present in this SKU

PCI Express Root Port 8 Shadowed by x2/x4 port

PCI Express Root Port 8 Lane configured as USB/SATA/UFS/GbE

PCI Express Root Port 9

PCI Express Root Port 9 Not present in this SKU

PCI Express Root Port 9 Shadowed by x2/x4 port

PCI Express Root Port 9 Lane configured as USB/SATA/UFS/GbE

PCI Express Root Port 10

PCI Express Root Port 10 Not present in this SKU

PCI Express Root Port 10 Shadowed by x2/x4 port

PCI Express Root Port 10 Lane configured as USB/SATA/UFS/GbE

PCI Express Root Port 11

PCI Express Root Port 11 Not present in this SKU

PCI Express Root Port 11 Shadowed by x2/x4 port

PCI Express Root Port 11 Lane configured as USB/SATA/UFS/GbE

PCI Express Root Port 12

PCI Express Root Port 12 Not present in this SKU

PCI Express Root Port 12 Shadowed by x2/x4 port

PCI Express Root Port 12 Lane configured as USB/SATA/UFS/GbE

PCI Express Root Port 13

PCI Express Root Port 13 Not present in this SKU

PCI Express Root Port 13 Shadowed by x2/x4 port

PCI Express Root Port 13 Lane configured as USB/SATA/UFS/GbE

PCI Express Root Port 14

PCI Express Root Port 14 Not present in this SKU

PCI Express Root Port 14 Shadowed by x2/x4 port

PCI Express Root Port 14 Lane configured as USB/SATA/UFS/GbE

PCI Express Root Port 15

PCI Express Root Port 15 Not present in this SKU

PCI Express Root Port 15 Shadowed by x2/x4 port

PCI Express Root Port 15 Lane configured as USB/SATA/UFS/GbE

PCI Express Root Port 16

PCI Express Root Port 16 Not present in this SKU

PCI Express Root Port 16 Shadowed by x2/x4 port

PCI Express Root Port 16 Lane configured as USB/SATA/UFS/GbE

PCI Express Root Port 17

PCI Express Root Port 17 Not present in this SKU

PCI Express Root Port 17 Shadowed by x2/x4 port

PCI Express Root Port 17 Lane configured as USB/SATA/UFS/GbE

PCI Express Root Port 18

PCI Express Root Port 18 Not present in this SKU

PCI Express Root Port 18 Shadowed by x2/x4 port

PCI Express Root Port 18 Lane configured as USB/SATA/UFS/GbE

PCI Express Root Port 19

PCI Express Root Port 19 Not present in this SKU

PCI Express Root Port 19 Shadowed by x2/x4 port

PCI Express Root Port 19 Lane configured as USB/SATA/UFS/GbE

PCI Express Root Port 20

PCI Express Root Port 20 Not present in this SKU

PCI Express Root Port 20 Shadowed by x2/x4 port

PCI Express Root Port 20 Lane configured as USB/SATA/UFS/GbE

PCI Express Root Port 21

PCI Express Root Port 21 Not present in this SKU

PCI Express Root Port 21 Shadowed by x2/x4 port

PCI Express Root Port 21 Lane configured as USB/SATA/UFS/GbE

PCI Express Root Port 22

PCI Express Root Port 22 Not present in this SKU

PCI Express Root Port 22 Shadowed by x2/x4 port

PCI Express Root Port 22 Lane configured as USB/SATA/UFS/GbE

PCI Express Root Port 23

PCI Express Root Port 23 Not present in this SKU

PCI Express Root Port 23 Shadowed by x2/x4 port

PCI Express Root Port 23 Lane configured as USB/SATA/UFS/GbE

PCI Express Root Port 24

PCI Express Root Port 24 Not present in this SKU

PCI Express Root Port 24 Shadowed by x2/x4 port

PCI Express Root Port 24 Lane configured as USB/SATA/UFS/GbE

PCIE clocks

USB Configuration

xDCI Support

Enable/Disable xDCI (USB OTG Device).

USB2 PHY Sus Well Power Gating

Select 'Enabled' to enable SUS Well PG for USB2 PHY. This option has no effect on PCH-H

USB3 Link Compliance

Enable/Disable USB3 Link Compliance

XHCI LTR Mode

Enable/Disable XHCI LTR Mode

USB PDO Programming

Select 'Enabled' if Port Disable Override functionality is used.

USB Overcurrent

Select 'Disabled' for pin-based debug. If pin-based debug is enabled but USB overcurrent is not disabled, USB DbC does not work.

USB Overcurrent Lock

Select 'Enabled' if Overcurrent functionality is used. Enabling this will make xHCI controller consume the Overcurrent mapping data

USB Port Disable Override

Selectively Enable/Disable the corresponding USB port from reporting a Device Connection to the controller.

USB SS Physical Connector #0

Enable/Disable this USB Physical Connector (physical port). Once disabled, any USB devices plug into the connector will not be detected by BIOS or OS.

USB SS Physical Connector #1

Enable/Disable this USB Physical Connector (physical port). Once disabled, any USB devices plug into the connector will not be detected by BIOS or OS.

USB SS Physical Connector #2

Enable/Disable this USB Physical Connector (physical port). Once disabled, any USB devices plug into the connector will not be detected by BIOS or OS.

USB SS Physical Connector #3

Enable/Disable this USB Physical Connector (physical port). Once disabled, any USB devices plug into the connector will not be detected by BIOS or OS.

USB SS Physical Connector #4

Enable/Disable this USB Physical Connector (physical port). Once disabled, any USB devices plug into the connector will not be detected by BIOS or OS.

USB SS Physical Connector #5

Enable/Disable this USB Physical Connector (physical port). Once disabled, any USB devices plug into the connector will not be detected by BIOS or OS.

USB SS Physical Connector #6

Enable/Disable this USB Physical Connector (physical port). Once disabled, any USB devices plug into the connector will not be detected by BIOS or OS.

USB SS Physical Connector #7

Enable/Disable this USB Physical Connector (physical port). Once disabled, any USB devices plug into the connector will not be detected by BIOS or OS.

USB SS Physical Connector #8

Enable/Disable this USB Physical Connector (physical port). Once disabled, any USB devices plug into the connector will not be detected by BIOS or OS.

USB SS Physical Connector #9

Enable/Disable this USB Physical Connector (physical port). Once disabled, any USB devices plug into the connector will not be detected by BIOS or OS.

USB HS Physical Connector #0

Enable/Disable this USB Physical Connector (physical port). Once disabled, any USB devices plug into the connector will not be detected by BIOS or OS.

USB HS Physical Connector #1

Enable/Disable this USB Physical Connector (physical port). Once disabled, any USB devices plug into the connector will not be detected by BIOS or OS.

USB HS Physical Connector #2

Enable/Disable this USB Physical Connector (physical port). Once disabled, any USB devices plug into the connector will not be detected by BIOS or OS.

USB HS Physical Connector #3

Enable/Disable this USB Physical Connector (physical port). Once disabled, any USB devices plug into the connector will not be detected by BIOS or OS.

USB HS Physical Connector #4

Enable/Disable this USB Physical Connector (physical port). Once disabled, any USB devices plug into the connector will not be detected by BIOS or OS.

USB HS Physical Connector #5

Enable/Disable this USB Physical Connector (physical port). Once disabled, any USB devices plug into the connector will not be detected by BIOS or OS.

USB HS Physical Connector #6

Enable/Disable this USB Physical Connector (physical port). Once disabled, any USB devices plug into the connector will not be detected by BIOS or OS.

USB HS Physical Connector #7

Enable/Disable this USB Physical Connector (physical port). Once disabled, any USB devices plug into the connector will not be detected by BIOS or OS.

USB HS Physical Connector #8

Enable/Disable this USB Physical Connector (physical port). Once disabled, any USB devices plug into the connector will not be detected by BIOS or OS.

USB HS Physical Connector #9

Enable/Disable this USB Physical Connector (physical port). Once disabled, any USB devices plug into the connector will not be detected by BIOS or OS.

USB HS Physical Connector #10

Enable/Disable this USB Physical Connector (physical port). Once disabled, any USB devices plug into the connector will not be detected by BIOS or OS.

USB HS Physical Connector #11

Enable/Disable this USB Physical Connector (physical port). Once disabled, any USB devices plug into the connector will not be detected by BIOS or OS.

USB HS Physical Connector #12

Enable/Disable this USB Physical Connector (physical port). Once disabled, any USB devices plug into the connector will not be detected by BIOS or OS.

USB HS Physical Connector #13

Enable/Disable this USB Physical Connector (physical port). Once disabled, any USB devices plug into the connector will not be detected by BIOS or OS.

USB Sensor Hub

USB Sensor Hub enable/disable

SATA And RST Configuration

SATA Controller(s)

Enable/Disable SATA Device.

SATA Mode Selection

Determines how SATA controller(s) operate.

Sata Interrupt Selection

Select which interrupt will be available to OS. This option only takes effect if SATA controller is in RAID mode

PCIe Storage Dev On Port 1

Enable/Disable RST Pcie Storage Remapping

PCIe Storage Dev On Port 2

Enable/Disable RST Pcie Storage Remapping

PCIe Storage Dev On Port 3

Enable/Disable RST Pcie Storage Remapping

PCIe Storage Dev On Port 4

Enable/Disable RST Pcie Storage Remapping

PCIe Storage Dev On Port 5

Enable/Disable RST Pcie Storage Remapping

PCIe Storage Dev On Port 6

Enable/Disable RST Pcie Storage Remapping

PCIe Storage Dev On Port 7

Enable/Disable RST Pcie Storage Remapping

PCIe Storage Dev On Port 8

Enable/Disable RST Pcie Storage Remapping

PCIe Storage Dev On Port 9

Enable/Disable RST Pcie Storage Remapping

PCIe Storage Dev On Port 10

Enable/Disable RST Pcie Storage Remapping

PCIe Storage Dev On Port 11

Enable/Disable RST Pcie Storage Remapping

PCIe Storage Dev On Port 12

Enable/Disable RST Pcie Storage Remapping

PCIe Storage Dev On Port 13

Enable/Disable RST Pcie Storage Remapping

PCIe Storage Dev On Port 14

Enable/Disable RST Pcie Storage Remapping

PCIe Storage Dev On Port 15

Enable/Disable RST Pcie Storage Remapping

PCIe Storage Dev On Port 16

Enable/Disable RST Pcie Storage Remapping

PCIe Storage Dev On Port 17

Enable/Disable RST Pcie Storage Remapping

PCIe Storage Dev On Port 18

Enable/Disable RST Pcie Storage Remapping

PCIe Storage Dev On Port 19

Enable/Disable RST Pcie Storage Remapping

PCIe Storage Dev On Port 20

Enable/Disable RST Pcie Storage Remapping

PCIe Storage Dev On Port 21

Enable/Disable RST Pcie Storage Remapping

PCIe Storage Dev On Port 22

Enable/Disable RST Pcie Storage Remapping

PCIe Storage Dev On Port 23

Enable/Disable RST Pcie Storage Remapping

PCIe Storage Dev On Port 24

Enable/Disable RST Pcie Storage Remapping

SATA Test Mode

Test Mode Enable/Disable (Loop Back).

RAID Device ID

Choose RAID Device ID

Software Feature Mask Configuration

Aggressive LPM Support

Enable PCH to aggressively enter link power state.

Serial ATA Port 0 Empty

Software Preserve Unknown

Port 0

Enable or Disable SATA Port

Hot Plug

Designates this port as Hot Pluggable.

Configured as eSATA Hot Plug supported

External

Marks this port as external.

Mechanical Presence Switch

Controls reporting if this port has an Mechanical Presence Switch. Note: Requires hardware support.

Spin Up Device

If enabled for any of ports Staggerred Spin Up will be performed and only the drives which have this option enabled will spin up at boot. Otherwise all drives spin up at boot.

SATA Device Type

Identify the SATA port is connected to Solid State Drive or Hard Disk Drive

Topology

Identify the SATA Topology if it is Default or ISATA or Flex or DirectConnect or M2

SATA Port 0 DevSlp

Enable/Disable SATA Port 0 DevSlp. For DevSlp to work, both hard drive and SATA port need to support DevSlp function, otherwise an unexpected behavior might happen. Please check board design before enabling it.

DITO Configuration

Enable/Disable DITO Configuration

DITO Value

DM Value

Serial ATA Port 1 Empty

Software Preserve Unknown

Port 1

Enable or Disable SATA Port

Hot Plug

Designates this port as Hot Pluggable.

Configured as eSATA Hot Plug supported

External

Marks this port as external.

Mechanical Presence Switch

Controls reporting if this port has an Mechanical Presence Switch. Note: Requires hardware support.

Spin Up Device

If enabled for any of ports Staggerred Spin Up will be performed and only the drives which have this option enabled will spin up at boot. Otherwise all drives spin up at boot.

SATA Device Type

Identify the SATA port is connected to Solid State Drive or Hard Disk Drive

Topology

Identify the SATA Topology if it is Default or ISATA or Flex or DirectConnect or M2

SATA Port 1 DevSlp

Enable/Disable SATA Port 1 DevSlp. For DevSlp to work, both hard drive and SATA port need to support DevSlp function, otherwise an unexpected behavior might happen. Please check board design before enabling it.

DITO Configuration

Enable/Disable DITO Configuration

DITO Value

DM Value

Serial ATA Port 2 Empty

Software Preserve Unknown

Port 2

Enable or Disable SATA Port

Hot Plug

Designates this port as Hot Pluggable.

Configured as eSATA Hot Plug supported

External

Marks this port as external.

Mechanical Presence Switch

Controls reporting if this port has an Mechanical Presence Switch. Note: Requires hardware support.

Spin Up Device

If enabled for any of ports Staggerred Spin Up will be performed and only the drives which have this option enabled will spin up at boot. Otherwise all drives spin up at boot.

SATA Device Type

Identify the SATA port is connected to Solid State Drive or Hard Disk Drive

Topology

Identify the SATA Topology if it is Default or ISATA or Flex or DirectConnect or M2

SATA Port 2 DevSlp

Enable/Disable SATA Port 2 DevSlp. For DevSlp to work, both hard drive and SATA port need to support DevSlp function, otherwise an unexpected behavior might happen. Please check board design before enabling it.

DITO Configuration

Enable/Disable DITO Configuration

DITO Value

DM Value

Serial ATA Port 3 Empty

Software Preserve Unknown

Port 3

Enable or Disable SATA Port

Hot Plug

Designates this port as Hot Pluggable.

Configured as eSATA Hot Plug supported

External

Marks this port as external.

Mechanical Presence Switch

Controls reporting if this port has an Mechanical Presence Switch. Note: Requires hardware support.

Spin Up Device

If enabled for any of ports Staggerred Spin Up will be performed and only the drives which have this option enabled will spin up at boot. Otherwise all drives spin up at boot.

SATA Device Type

Identify the SATA port is connected to Solid State Drive or Hard Disk Drive

Topology

Identify the SATA Topology if it is Default or ISATA or Flex or DirectConnect or M2

SATA Port 3 DevSlp

Enable/Disable SATA Port 3 DevSlp. For DevSlp to work, both hard drive and SATA port need to support DevSlp function, otherwise an unexpected behavior might happen. Please check board design before enabling it.

DITO Configuration

Enable/Disable DITO Configuration

DITO Value

DM Value

Serial ATA Port 4 Empty

Software Preserve Unknown

Port 4

Enable or Disable SATA Port

Hot Plug

Designates this port as Hot Pluggable.

Configured as eSATA Hot Plug supported

External

Marks this port as external.

Mechanical Presence Switch

Controls reporting if this port has an Mechanical Presence Switch. Note: Requires hardware support.

Spin Up Device

If enabled for any of ports Staggerred Spin Up will be performed and only the drives which have this option enabled will spin up at boot. Otherwise all drives spin up at boot.

SATA Device Type

Identify the SATA port is connected to Solid State Drive or Hard Disk Drive

Topology

Identify the SATA Topology if it is Default or ISATA or Flex or DirectConnect or M2

SATA Port 4 DevSlp

Enable/Disable SATA Port 4 DevSlp. For DevSlp to work, both hard drive and SATA port need to support DevSlp function, otherwise an unexpected behavior might happen. Please check board design before enabling it.

DITO Configuration

Enable/Disable DITO Configuration

DITO Value

DM Value

Serial ATA Port 5 Empty

Software Preserve Unknown

Port 5

Enable or Disable SATA Port

Hot Plug

Designates this port as Hot Pluggable.

Configured as eSATA Hot Plug supported

External

Marks this port as external.

Mechanical Presence Switch

Controls reporting if this port has an Mechanical Presence Switch. Note: Requires hardware support.

Spin Up Device

If enabled for any of ports Staggerred Spin Up will be performed and only the drives which have this option enabled will spin up at boot. Otherwise all drives spin up at boot.

SATA Device Type

Identify the SATA port is connected to Solid State Drive or Hard Disk Drive

Topology

Identify the SATA Topology if it is Default or ISATA or Flex or DirectConnect or M2

SATA Port 5 DevSlp

Enable/Disable SATA Port 5 DevSlp. For DevSlp to work, both hard drive and SATA port need to support DevSlp function, otherwise an unexpected behavior might happen. Please check board design before enabling it.

DITO Configuration

Enable/Disable DITO Configuration

DITO Value

DM Value

Serial ATA Port 6 Empty

Software Preserve Unknown

Port 6

Enable or Disable SATA Port

Hot Plug

Designates this port as Hot Pluggable.

Configured as eSATA Hot Plug supported

External

Marks this port as external.

Mechanical Presence Switch

Controls reporting if this port has an Mechanical Presence Switch. Note: Requires hardware support.

Spin Up Device

If enabled for any of ports Staggerred Spin Up will be performed and only the drives which have this option enabled will spin up at boot. Otherwise all drives spin up at boot.

SATA Device Type

Identify the SATA port is connected to Solid State Drive or Hard Disk Drive

Topology

Identify the SATA Topology if it is Default or ISATA or Flex or DirectConnect or M2

SATA Port 6 DevSlp

Enable/Disable SATA Port 6 DevSlp. For DevSlp to work, both hard drive and SATA port need to support DevSlp function, otherwise an unexpected behavior might happen. Please check board design before enabling it.

DITO Configuration

Enable/Disable DITO Configuration

DITO Value

DM Value

Serial ATA Port 7 Empty

Software Preserve Unknown

Port 7

Enable or Disable SATA Port

Hot Plug

Designates this port as Hot Pluggable.

Configured as eSATA Hot Plug supported

External

Marks this port as external.

Mechanical Presence Switch

Controls reporting if this port has an Mechanical Presence Switch. Note: Requires hardware support.

Spin Up Device

If enabled for any of ports Staggerred Spin Up will be performed and only the drives which have this option enabled will spin up at boot. Otherwise all drives spin up at boot.

SATA Device Type

Identify the SATA port is connected to Solid State Drive or Hard Disk Drive

Topology

Identify the SATA Topology if it is Default or ISATA or Flex or DirectConnect or M2

SATA Port 7 DevSlp

Enable/Disable SATA Port 7 DevSlp. For DevSlp to work, both hard drive and SATA port need to support DevSlp function, otherwise an unexpected behavior might happen. Please check board design before enabling it.

DITO Configuration

Enable/Disable DITO Configuration

DITO Value

DM Value

Software Feature Mask Configuration

HDD Unlock

If enabled, indicates that the HDD password unlock in the OS is enabled.

LED Locate

If enabled, indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS.

RAID0

Enable/Disable RAID0 feature.

RAID1

Enable/Disable RAID1 feature.

RAID10

Enable/Disable RAID10 feature.

RAID5

Enable/Disable RAID5 feature.

Intel Rapid Recovery Technology

Enable/Disable Intel Rapid Recovery Technology.

OROM UI and BANNER

If enabled, then the OROM UI is shown. Otherwise, no OROM banner or information will be displayed if all disks and RAID volumes are Normal.

IRRT Only on eSATA

If enabled, then only IRRT volumes can span internal and eSATA drives. If disabled, then any RAID volume can span internal and eSATA drives.

Smart Response Technology

Enabled/Disable Smart Response Technology feature

OROM UI Normal Delay

Select the delay time of the OROM UI Splash Screen in a normal status

RST Force Form

Enable/Disable Form for Intel Rapid Storage Technology.

System Acceleration with Intel(R) Optane(TM) Memory

Enable/Disable System Acceleration with Intel(R) Optane(TM) Memory feature.

CPU Attached Storage

Enable/Disable CPU Attached Storage feature

PCIe EQ override Enabled

Choose your own PCIe EQ settings, only for users who have a thorough understanding of equalization process

PCIe EQ method

Choose PCIe EQ method

PCIe EQ mode

Choose EQ mode. Preset mode - root port will use presets during EQ process, Coefficient mode - root port will use coefficients during EQ process

EQ PH1 downstream port transmitter preset

Choose the value of the preset that will be used during phase 1 of the equalization

EQ PH1 upstream port transmitter preset

Choose the value of the preset that will be used during phase 1 of the equalization

Enable EQ phase 2 local transmitter override Enabled

EQ Phase 2 local transmitter override can be used to debug issues with PCI devices equalization.

EQ Phase 2 local transmitter override preset

Select preset which will be used during phase 2 of the PCIe EQ process

Number of presets or coefficients used during phase 3

Select how many presets or coefficients will be used during phase 3 of EQ. Please not that you have to set all of the list entries to valid values. The interpretation of this field depends on PCIe EQ mode

Preset 0

Choose the target preset value

Preset 1

Choose the target preset value

Preset 2

Choose the target preset value

Preset 3

Choose the target preset value

Preset 4

Choose the target preset value

Preset 5

Choose the target preset value

Preset 6

Choose the target preset value

Preset 7

Choose the target preset value

Preset 8

Choose the target preset value

Preset 9

Choose the target preset value

Preset 10

Choose the target preset value

Pre-cursor coefficient 0

Choose the target pre-cursor coefficient value

Post-cursor coefficient 0

Choose the target post-curosr coefficient value

Pre-cursor coefficient 1

Choose the target pre-cursor coefficient value

Post-cursor coefficient 1

Choose the target post-curosr coefficient value

Pre-cursor coefficient 2

Choose the target pre-cursor coefficient value

Post-cursor coefficient 2

Choose the target post-curosr coefficient value

Pre-cursor coefficient 3

Choose the target pre-cursor coefficient value

Post-cursor coefficient 3

Choose the target post-curosr coefficient value

Pre-cursor coefficient 4

Choose the target pre-cursor coefficient value

Post-cursor coefficient 4

Choose the target post-curosr coefficient value

Pre-cursor coefficient 5

Choose the target pre-cursor coefficient value

Post-cursor coefficient 5

Choose the target post-curosr coefficient value

Pre-cursor coefficient 6

Choose the target pre-cursor coefficient value

Post-cursor coefficient 6

Choose the target post-curosr coefficient value

Pre-cursor coefficient 7

Choose the target pre-cursor coefficient value

Post-cursor coefficient 7

Choose the target post-curosr coefficient value

Pre-cursor coefficient 8

Choose the target pre-cursor coefficient value

Post-cursor coefficient 8

Choose the target post-curosr coefficient value

Pre-cursor coefficient 9

Choose the target pre-cursor coefficient value

Post-cursor coefficient 9

Choose the target post-curosr coefficient value

PCI Express Root Port 1

Control the PCI Express Root Port.

Connection Type

Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.

ASPM

PCI Express Active State Power Management settings.

L1 Substates

PCI Express L1 Substates settings.

ACS

Enable/Disable Access Control Services Extended Capability

PTM

Enable/Disable Precision Time Measurement

DPC

Enable/Disable Downstream Port Containment

EDPC

Enable/Disable Rootport extensions for Downstream Port Containment

URR

PCI Express Unsupported Request Reporting Enable/Disable.

FER

PCI Express Device Fatal Error Reporting Enable/Disable.

NFER

PCI Express Device Non-Fatal Error Reporting Enable/Disable.

CER

PCI Express Device Correctable Error Reporting Enable/Disable.

SEFE

Root PCI Express System Error on Fatal Error Enable/Disable.

SENFE

Root PCI Express System Error on Non-Fatal Error Enable/Disable.

SECE

Root PCI Express System Error on Correctable Error Enable/Disable.

PME SCI

PCI Express PME SCI Enable/Disable.

Hot Plug

PCI Express Hot Plug Enable/Disable.

Advanced Error Reporting

Advanced Error Reporting Enable/Disable.

PCIe Speed

Configure PCIe Speed

Transmitter Half Swing

Transmitter Half Swing Enable/Disable.

Detect Timeout

The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.

Extra Bus Reserved

Extra Bus Reserved (0-7) for bridges behind this Root Bridge.

Reserved Memory

Reserved Memory for this Root Bridge (1-20) MB

Reserved I/O

Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge.

PCH PCIe LTR Configuration

LTR

PCH PCIE Latency Reporting Enable/Disable

Snoop Latency Override

Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Snoop Latency Value

LTR Snoop Latency value of PCH PCIE

Snoop Latency Multiplier

LTR Snoop Latency Multiplier of PCH PCIE

Non Snoop Latency Override

Non Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Non Snoop Latency Value

LTR Non Snoop Latency value of PCH PCIE

Non Snoop Latency Multiplier

LTR Non Snoop Latency Multiplier of PCH PCIE

Force LTR Override

Force LTR Override for PCH PCIE. Disabled: LTR override values will not be forced. Enable: LTR override values will be forced and LTR messages from the device will be ignored.

LTR Lock

PCIE LTR Configuration Lock

PCI Express Root Port 2

Control the PCI Express Root Port.

Connection Type

Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.

ASPM

PCI Express Active State Power Management settings.

L1 Substates

PCI Express L1 Substates settings.

ACS

Enable/Disable Access Control Services Extended Capability

PTM

Enable/Disable Precision Time Measurement

DPC

Enable/Disable Downstream Port Containment

EDPC

Enable/Disable Rootport extensions for Downstream Port Containment

URR

PCI Express Unsupported Request Reporting Enable/Disable.

FER

PCI Express Device Fatal Error Reporting Enable/Disable.

NFER

PCI Express Device Non-Fatal Error Reporting Enable/Disable.

CER

PCI Express Device Correctable Error Reporting Enable/Disable.

SEFE

Root PCI Express System Error on Fatal Error Enable/Disable.

SENFE

Root PCI Express System Error on Non-Fatal Error Enable/Disable.

SECE

Root PCI Express System Error on Correctable Error Enable/Disable.

PME SCI

PCI Express PME SCI Enable/Disable.

Hot Plug

PCI Express Hot Plug Enable/Disable.

Advanced Error Reporting

Advanced Error Reporting Enable/Disable.

PCIe Speed

Configure PCIe Speed

Transmitter Half Swing

Transmitter Half Swing Enable/Disable.

Detect Timeout

The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.

Extra Bus Reserved

Extra Bus Reserved (0-7) for bridges behind this Root Bridge.

Reserved Memory

Reserved Memory for this Root Bridge (1-20) MB

Reserved I/O

Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge.

PCH PCIe LTR Configuration

LTR

PCH PCIE Latency Reporting Enable/Disable

Snoop Latency Override

Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Snoop Latency Value

LTR Snoop Latency value of PCH PCIE

Snoop Latency Multiplier

LTR Snoop Latency Multiplier of PCH PCIE

Non Snoop Latency Override

Non Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Non Snoop Latency Value

LTR Non Snoop Latency value of PCH PCIE

Non Snoop Latency Multiplier

LTR Non Snoop Latency Multiplier of PCH PCIE

Force LTR Override

Force LTR Override for PCH PCIE. Disabled: LTR override values will not be forced. Enable: LTR override values will be forced and LTR messages from the device will be ignored.

LTR Lock

PCIE LTR Configuration Lock

PCI Express Root Port 3

Control the PCI Express Root Port.

Connection Type

Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.

ASPM

PCI Express Active State Power Management settings.

L1 Substates

PCI Express L1 Substates settings.

ACS

Enable/Disable Access Control Services Extended Capability

PTM

Enable/Disable Precision Time Measurement

DPC

Enable/Disable Downstream Port Containment

EDPC

Enable/Disable Rootport extensions for Downstream Port Containment

URR

PCI Express Unsupported Request Reporting Enable/Disable.

FER

PCI Express Device Fatal Error Reporting Enable/Disable.

NFER

PCI Express Device Non-Fatal Error Reporting Enable/Disable.

CER

PCI Express Device Correctable Error Reporting Enable/Disable.

SEFE

Root PCI Express System Error on Fatal Error Enable/Disable.

SENFE

Root PCI Express System Error on Non-Fatal Error Enable/Disable.

SECE

Root PCI Express System Error on Correctable Error Enable/Disable.

PME SCI

PCI Express PME SCI Enable/Disable.

Hot Plug

PCI Express Hot Plug Enable/Disable.

Advanced Error Reporting

Advanced Error Reporting Enable/Disable.

PCIe Speed

Configure PCIe Speed

Transmitter Half Swing

Transmitter Half Swing Enable/Disable.

Detect Timeout

The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.

Extra Bus Reserved

Extra Bus Reserved (0-7) for bridges behind this Root Bridge.

Reserved Memory

Reserved Memory for this Root Bridge (1-20) MB

Reserved I/O

Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge.

PCH PCIe LTR Configuration

LTR

PCH PCIE Latency Reporting Enable/Disable

Snoop Latency Override

Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Snoop Latency Value

LTR Snoop Latency value of PCH PCIE

Snoop Latency Multiplier

LTR Snoop Latency Multiplier of PCH PCIE

Non Snoop Latency Override

Non Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Non Snoop Latency Value

LTR Non Snoop Latency value of PCH PCIE

Non Snoop Latency Multiplier

LTR Non Snoop Latency Multiplier of PCH PCIE

Force LTR Override

Force LTR Override for PCH PCIE. Disabled: LTR override values will not be forced. Enable: LTR override values will be forced and LTR messages from the device will be ignored.

LTR Lock

PCIE LTR Configuration Lock

PCI Express Root Port 4

Control the PCI Express Root Port.

Connection Type

Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.

ASPM

PCI Express Active State Power Management settings.

L1 Substates

PCI Express L1 Substates settings.

ACS

Enable/Disable Access Control Services Extended Capability

PTM

Enable/Disable Precision Time Measurement

DPC

Enable/Disable Downstream Port Containment

EDPC

Enable/Disable Rootport extensions for Downstream Port Containment

URR

PCI Express Unsupported Request Reporting Enable/Disable.

FER

PCI Express Device Fatal Error Reporting Enable/Disable.

NFER

PCI Express Device Non-Fatal Error Reporting Enable/Disable.

CER

PCI Express Device Correctable Error Reporting Enable/Disable.

SEFE

Root PCI Express System Error on Fatal Error Enable/Disable.

SENFE

Root PCI Express System Error on Non-Fatal Error Enable/Disable.

SECE

Root PCI Express System Error on Correctable Error Enable/Disable.

PME SCI

PCI Express PME SCI Enable/Disable.

Hot Plug

PCI Express Hot Plug Enable/Disable.

Advanced Error Reporting

Advanced Error Reporting Enable/Disable.

PCIe Speed

Configure PCIe Speed

Transmitter Half Swing

Transmitter Half Swing Enable/Disable.

Detect Timeout

The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.

Extra Bus Reserved

Extra Bus Reserved (0-7) for bridges behind this Root Bridge.

Reserved Memory

Reserved Memory for this Root Bridge (1-20) MB

Reserved I/O

Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge.

PCH PCIe LTR Configuration

LTR

PCH PCIE Latency Reporting Enable/Disable

Snoop Latency Override

Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Snoop Latency Value

LTR Snoop Latency value of PCH PCIE

Snoop Latency Multiplier

LTR Snoop Latency Multiplier of PCH PCIE

Non Snoop Latency Override

Non Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Non Snoop Latency Value

LTR Non Snoop Latency value of PCH PCIE

Non Snoop Latency Multiplier

LTR Non Snoop Latency Multiplier of PCH PCIE

Force LTR Override

Force LTR Override for PCH PCIE. Disabled: LTR override values will not be forced. Enable: LTR override values will be forced and LTR messages from the device will be ignored.

LTR Lock

PCIE LTR Configuration Lock

PCI Express Root Port 5

Control the PCI Express Root Port.

Connection Type

Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.

ASPM

PCI Express Active State Power Management settings.

L1 Substates

PCI Express L1 Substates settings.

ACS

Enable/Disable Access Control Services Extended Capability

PTM

Enable/Disable Precision Time Measurement

DPC

Enable/Disable Downstream Port Containment

EDPC

Enable/Disable Rootport extensions for Downstream Port Containment

URR

PCI Express Unsupported Request Reporting Enable/Disable.

FER

PCI Express Device Fatal Error Reporting Enable/Disable.

NFER

PCI Express Device Non-Fatal Error Reporting Enable/Disable.

CER

PCI Express Device Correctable Error Reporting Enable/Disable.

SEFE

Root PCI Express System Error on Fatal Error Enable/Disable.

SENFE

Root PCI Express System Error on Non-Fatal Error Enable/Disable.

SECE

Root PCI Express System Error on Correctable Error Enable/Disable.

PME SCI

PCI Express PME SCI Enable/Disable.

Hot Plug

PCI Express Hot Plug Enable/Disable.

Advanced Error Reporting

Advanced Error Reporting Enable/Disable.

PCIe Speed

Configure PCIe Speed

Transmitter Half Swing

Transmitter Half Swing Enable/Disable.

Detect Timeout

The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.

Extra Bus Reserved

Extra Bus Reserved (0-7) for bridges behind this Root Bridge.

Reserved Memory

Reserved Memory for this Root Bridge (1-20) MB

Reserved I/O

Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge.

PCH PCIe LTR Configuration

LTR

PCH PCIE Latency Reporting Enable/Disable

Snoop Latency Override

Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Snoop Latency Value

LTR Snoop Latency value of PCH PCIE

Snoop Latency Multiplier

LTR Snoop Latency Multiplier of PCH PCIE

Non Snoop Latency Override

Non Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Non Snoop Latency Value

LTR Non Snoop Latency value of PCH PCIE

Non Snoop Latency Multiplier

LTR Non Snoop Latency Multiplier of PCH PCIE

Force LTR Override

Force LTR Override for PCH PCIE. Disabled: LTR override values will not be forced. Enable: LTR override values will be forced and LTR messages from the device will be ignored.

LTR Lock

PCIE LTR Configuration Lock

PCI Express Root Port 6

Control the PCI Express Root Port.

Connection Type

Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.

ASPM

PCI Express Active State Power Management settings.

L1 Substates

PCI Express L1 Substates settings.

ACS

Enable/Disable Access Control Services Extended Capability

PTM

Enable/Disable Precision Time Measurement

DPC

Enable/Disable Downstream Port Containment

EDPC

Enable/Disable Rootport extensions for Downstream Port Containment

URR

PCI Express Unsupported Request Reporting Enable/Disable.

FER

PCI Express Device Fatal Error Reporting Enable/Disable.

NFER

PCI Express Device Non-Fatal Error Reporting Enable/Disable.

CER

PCI Express Device Correctable Error Reporting Enable/Disable.

SEFE

Root PCI Express System Error on Fatal Error Enable/Disable.

SENFE

Root PCI Express System Error on Non-Fatal Error Enable/Disable.

SECE

Root PCI Express System Error on Correctable Error Enable/Disable.

PME SCI

PCI Express PME SCI Enable/Disable.

Hot Plug

PCI Express Hot Plug Enable/Disable.

Advanced Error Reporting

Advanced Error Reporting Enable/Disable.

PCIe Speed

Configure PCIe Speed

Transmitter Half Swing

Transmitter Half Swing Enable/Disable.

Detect Timeout

The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.

Extra Bus Reserved

Extra Bus Reserved (0-7) for bridges behind this Root Bridge.

Reserved Memory

Reserved Memory for this Root Bridge (1-20) MB

Reserved I/O

Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge.

PCH PCIe LTR Configuration

LTR

PCH PCIE Latency Reporting Enable/Disable

Snoop Latency Override

Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Snoop Latency Value

LTR Snoop Latency value of PCH PCIE

Snoop Latency Multiplier

LTR Snoop Latency Multiplier of PCH PCIE

Non Snoop Latency Override

Non Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Non Snoop Latency Value

LTR Non Snoop Latency value of PCH PCIE

Non Snoop Latency Multiplier

LTR Non Snoop Latency Multiplier of PCH PCIE

Force LTR Override

Force LTR Override for PCH PCIE. Disabled: LTR override values will not be forced. Enable: LTR override values will be forced and LTR messages from the device will be ignored.

LTR Lock

PCIE LTR Configuration Lock

PCI Express Root Port 7

Control the PCI Express Root Port.

Connection Type

Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.

ASPM

PCI Express Active State Power Management settings.

L1 Substates

PCI Express L1 Substates settings.

ACS

Enable/Disable Access Control Services Extended Capability

PTM

Enable/Disable Precision Time Measurement

DPC

Enable/Disable Downstream Port Containment

EDPC

Enable/Disable Rootport extensions for Downstream Port Containment

URR

PCI Express Unsupported Request Reporting Enable/Disable.

FER

PCI Express Device Fatal Error Reporting Enable/Disable.

NFER

PCI Express Device Non-Fatal Error Reporting Enable/Disable.

CER

PCI Express Device Correctable Error Reporting Enable/Disable.

SEFE

Root PCI Express System Error on Fatal Error Enable/Disable.

SENFE

Root PCI Express System Error on Non-Fatal Error Enable/Disable.

SECE

Root PCI Express System Error on Correctable Error Enable/Disable.

PME SCI

PCI Express PME SCI Enable/Disable.

Hot Plug

PCI Express Hot Plug Enable/Disable.

Advanced Error Reporting

Advanced Error Reporting Enable/Disable.

PCIe Speed

Configure PCIe Speed

Transmitter Half Swing

Transmitter Half Swing Enable/Disable.

Detect Timeout

The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.

Extra Bus Reserved

Extra Bus Reserved (0-7) for bridges behind this Root Bridge.

Reserved Memory

Reserved Memory for this Root Bridge (1-20) MB

Reserved I/O

Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge.

PCH PCIe LTR Configuration

LTR

PCH PCIE Latency Reporting Enable/Disable

Snoop Latency Override

Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Snoop Latency Value

LTR Snoop Latency value of PCH PCIE

Snoop Latency Multiplier

LTR Snoop Latency Multiplier of PCH PCIE

Non Snoop Latency Override

Non Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Non Snoop Latency Value

LTR Non Snoop Latency value of PCH PCIE

Non Snoop Latency Multiplier

LTR Non Snoop Latency Multiplier of PCH PCIE

Force LTR Override

Force LTR Override for PCH PCIE. Disabled: LTR override values will not be forced. Enable: LTR override values will be forced and LTR messages from the device will be ignored.

LTR Lock

PCIE LTR Configuration Lock

PCI Express Root Port 8

Control the PCI Express Root Port.

Connection Type

Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.

ASPM

PCI Express Active State Power Management settings.

L1 Substates

PCI Express L1 Substates settings.

ACS

Enable/Disable Access Control Services Extended Capability

PTM

Enable/Disable Precision Time Measurement

DPC

Enable/Disable Downstream Port Containment

EDPC

Enable/Disable Rootport extensions for Downstream Port Containment

URR

PCI Express Unsupported Request Reporting Enable/Disable.

FER

PCI Express Device Fatal Error Reporting Enable/Disable.

NFER

PCI Express Device Non-Fatal Error Reporting Enable/Disable.

CER

PCI Express Device Correctable Error Reporting Enable/Disable.

SEFE

Root PCI Express System Error on Fatal Error Enable/Disable.

SENFE

Root PCI Express System Error on Non-Fatal Error Enable/Disable.

SECE

Root PCI Express System Error on Correctable Error Enable/Disable.

PME SCI

PCI Express PME SCI Enable/Disable.

Hot Plug

PCI Express Hot Plug Enable/Disable.

Advanced Error Reporting

Advanced Error Reporting Enable/Disable.

PCIe Speed

Configure PCIe Speed

Transmitter Half Swing

Transmitter Half Swing Enable/Disable.

Detect Timeout

The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.

Extra Bus Reserved

Extra Bus Reserved (0-7) for bridges behind this Root Bridge.

Reserved Memory

Reserved Memory for this Root Bridge (1-20) MB

Reserved I/O

Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge.

PCH PCIe LTR Configuration

LTR

PCH PCIE Latency Reporting Enable/Disable

Snoop Latency Override

Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Snoop Latency Value

LTR Snoop Latency value of PCH PCIE

Snoop Latency Multiplier

LTR Snoop Latency Multiplier of PCH PCIE

Non Snoop Latency Override

Non Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Non Snoop Latency Value

LTR Non Snoop Latency value of PCH PCIE

Non Snoop Latency Multiplier

LTR Non Snoop Latency Multiplier of PCH PCIE

Force LTR Override

Force LTR Override for PCH PCIE. Disabled: LTR override values will not be forced. Enable: LTR override values will be forced and LTR messages from the device will be ignored.

LTR Lock

PCIE LTR Configuration Lock

PCI Express Root Port 9

Control the PCI Express Root Port.

Connection Type

Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.

ASPM

PCI Express Active State Power Management settings.

L1 Substates

PCI Express L1 Substates settings.

ACS

Enable/Disable Access Control Services Extended Capability

PTM

Enable/Disable Precision Time Measurement

DPC

Enable/Disable Downstream Port Containment

EDPC

Enable/Disable Rootport extensions for Downstream Port Containment

URR

PCI Express Unsupported Request Reporting Enable/Disable.

FER

PCI Express Device Fatal Error Reporting Enable/Disable.

NFER

PCI Express Device Non-Fatal Error Reporting Enable/Disable.

CER

PCI Express Device Correctable Error Reporting Enable/Disable.

SEFE

Root PCI Express System Error on Fatal Error Enable/Disable.

SENFE

Root PCI Express System Error on Non-Fatal Error Enable/Disable.

SECE

Root PCI Express System Error on Correctable Error Enable/Disable.

PME SCI

PCI Express PME SCI Enable/Disable.

Hot Plug

PCI Express Hot Plug Enable/Disable.

Advanced Error Reporting

Advanced Error Reporting Enable/Disable.

PCIe Speed

Configure PCIe Speed

Transmitter Half Swing

Transmitter Half Swing Enable/Disable.

Detect Timeout

The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.

Extra Bus Reserved

Extra Bus Reserved (0-7) for bridges behind this Root Bridge.

Reserved Memory

Reserved Memory for this Root Bridge (1-20) MB

Reserved I/O

Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge.

PCH PCIe LTR Configuration

LTR

PCH PCIE Latency Reporting Enable/Disable

Snoop Latency Override

Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Snoop Latency Value

LTR Snoop Latency value of PCH PCIE

Snoop Latency Multiplier

LTR Snoop Latency Multiplier of PCH PCIE

Non Snoop Latency Override

Non Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Non Snoop Latency Value

LTR Non Snoop Latency value of PCH PCIE

Non Snoop Latency Multiplier

LTR Non Snoop Latency Multiplier of PCH PCIE

Force LTR Override

Force LTR Override for PCH PCIE. Disabled: LTR override values will not be forced. Enable: LTR override values will be forced and LTR messages from the device will be ignored.

LTR Lock

PCIE LTR Configuration Lock

PCI Express Root Port 10

Control the PCI Express Root Port.

Connection Type

Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.

ASPM

PCI Express Active State Power Management settings.

L1 Substates

PCI Express L1 Substates settings.

ACS

Enable/Disable Access Control Services Extended Capability

PTM

Enable/Disable Precision Time Measurement

DPC

Enable/Disable Downstream Port Containment

EDPC

Enable/Disable Rootport extensions for Downstream Port Containment

URR

PCI Express Unsupported Request Reporting Enable/Disable.

FER

PCI Express Device Fatal Error Reporting Enable/Disable.

NFER

PCI Express Device Non-Fatal Error Reporting Enable/Disable.

CER

PCI Express Device Correctable Error Reporting Enable/Disable.

SEFE

Root PCI Express System Error on Fatal Error Enable/Disable.

SENFE

Root PCI Express System Error on Non-Fatal Error Enable/Disable.

SECE

Root PCI Express System Error on Correctable Error Enable/Disable.

PME SCI

PCI Express PME SCI Enable/Disable.

Hot Plug

PCI Express Hot Plug Enable/Disable.

Advanced Error Reporting

Advanced Error Reporting Enable/Disable.

PCIe Speed

Configure PCIe Speed

Transmitter Half Swing

Transmitter Half Swing Enable/Disable.

Detect Timeout

The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.

Extra Bus Reserved

Extra Bus Reserved (0-7) for bridges behind this Root Bridge.

Reserved Memory

Reserved Memory for this Root Bridge (1-20) MB

Reserved I/O

Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge.

PCH PCIe LTR Configuration

LTR

PCH PCIE Latency Reporting Enable/Disable

Snoop Latency Override

Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Snoop Latency Value

LTR Snoop Latency value of PCH PCIE

Snoop Latency Multiplier

LTR Snoop Latency Multiplier of PCH PCIE

Non Snoop Latency Override

Non Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Non Snoop Latency Value

LTR Non Snoop Latency value of PCH PCIE

Non Snoop Latency Multiplier

LTR Non Snoop Latency Multiplier of PCH PCIE

Force LTR Override

Force LTR Override for PCH PCIE. Disabled: LTR override values will not be forced. Enable: LTR override values will be forced and LTR messages from the device will be ignored.

LTR Lock

PCIE LTR Configuration Lock

PCI Express Root Port 11

Control the PCI Express Root Port.

Connection Type

Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.

ASPM

PCI Express Active State Power Management settings.

L1 Substates

PCI Express L1 Substates settings.

ACS

Enable/Disable Access Control Services Extended Capability

PTM

Enable/Disable Precision Time Measurement

DPC

Enable/Disable Downstream Port Containment

EDPC

Enable/Disable Rootport extensions for Downstream Port Containment

URR

PCI Express Unsupported Request Reporting Enable/Disable.

FER

PCI Express Device Fatal Error Reporting Enable/Disable.

NFER

PCI Express Device Non-Fatal Error Reporting Enable/Disable.

CER

PCI Express Device Correctable Error Reporting Enable/Disable.

SEFE

Root PCI Express System Error on Fatal Error Enable/Disable.

SENFE

Root PCI Express System Error on Non-Fatal Error Enable/Disable.

SECE

Root PCI Express System Error on Correctable Error Enable/Disable.

PME SCI

PCI Express PME SCI Enable/Disable.

Hot Plug

PCI Express Hot Plug Enable/Disable.

Advanced Error Reporting

Advanced Error Reporting Enable/Disable.

PCIe Speed

Configure PCIe Speed

Transmitter Half Swing

Transmitter Half Swing Enable/Disable.

Detect Timeout

The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.

Extra Bus Reserved

Extra Bus Reserved (0-7) for bridges behind this Root Bridge.

Reserved Memory

Reserved Memory for this Root Bridge (1-20) MB

Reserved I/O

Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge.

PCH PCIe LTR Configuration

LTR

PCH PCIE Latency Reporting Enable/Disable

Snoop Latency Override

Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Snoop Latency Value

LTR Snoop Latency value of PCH PCIE

Snoop Latency Multiplier

LTR Snoop Latency Multiplier of PCH PCIE

Non Snoop Latency Override

Non Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Non Snoop Latency Value

LTR Non Snoop Latency value of PCH PCIE

Non Snoop Latency Multiplier

LTR Non Snoop Latency Multiplier of PCH PCIE

Force LTR Override

Force LTR Override for PCH PCIE. Disabled: LTR override values will not be forced. Enable: LTR override values will be forced and LTR messages from the device will be ignored.

LTR Lock

PCIE LTR Configuration Lock

PCI Express Root Port 12

Control the PCI Express Root Port.

Connection Type

Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.

ASPM

PCI Express Active State Power Management settings.

L1 Substates

PCI Express L1 Substates settings.

ACS

Enable/Disable Access Control Services Extended Capability

PTM

Enable/Disable Precision Time Measurement

DPC

Enable/Disable Downstream Port Containment

EDPC

Enable/Disable Rootport extensions for Downstream Port Containment

URR

PCI Express Unsupported Request Reporting Enable/Disable.

FER

PCI Express Device Fatal Error Reporting Enable/Disable.

NFER

PCI Express Device Non-Fatal Error Reporting Enable/Disable.

CER

PCI Express Device Correctable Error Reporting Enable/Disable.

SEFE

Root PCI Express System Error on Fatal Error Enable/Disable.

SENFE

Root PCI Express System Error on Non-Fatal Error Enable/Disable.

SECE

Root PCI Express System Error on Correctable Error Enable/Disable.

PME SCI

PCI Express PME SCI Enable/Disable.

Hot Plug

PCI Express Hot Plug Enable/Disable.

Advanced Error Reporting

Advanced Error Reporting Enable/Disable.

PCIe Speed

Configure PCIe Speed

Transmitter Half Swing

Transmitter Half Swing Enable/Disable.

Detect Timeout

The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.

Extra Bus Reserved

Extra Bus Reserved (0-7) for bridges behind this Root Bridge.

Reserved Memory

Reserved Memory for this Root Bridge (1-20) MB

Reserved I/O

Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge.

PCH PCIe LTR Configuration

LTR

PCH PCIE Latency Reporting Enable/Disable

Snoop Latency Override

Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Snoop Latency Value

LTR Snoop Latency value of PCH PCIE

Snoop Latency Multiplier

LTR Snoop Latency Multiplier of PCH PCIE

Non Snoop Latency Override

Non Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Non Snoop Latency Value

LTR Non Snoop Latency value of PCH PCIE

Non Snoop Latency Multiplier

LTR Non Snoop Latency Multiplier of PCH PCIE

Force LTR Override

Force LTR Override for PCH PCIE. Disabled: LTR override values will not be forced. Enable: LTR override values will be forced and LTR messages from the device will be ignored.

LTR Lock

PCIE LTR Configuration Lock

PCI Express Root Port 13

Control the PCI Express Root Port.

Connection Type

Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.

ASPM

PCI Express Active State Power Management settings.

L1 Substates

PCI Express L1 Substates settings.

ACS

Enable/Disable Access Control Services Extended Capability

PTM

Enable/Disable Precision Time Measurement

DPC

Enable/Disable Downstream Port Containment

EDPC

Enable/Disable Rootport extensions for Downstream Port Containment

URR

PCI Express Unsupported Request Reporting Enable/Disable.

FER

PCI Express Device Fatal Error Reporting Enable/Disable.

NFER

PCI Express Device Non-Fatal Error Reporting Enable/Disable.

CER

PCI Express Device Correctable Error Reporting Enable/Disable.

SEFE

Root PCI Express System Error on Fatal Error Enable/Disable.

SENFE

Root PCI Express System Error on Non-Fatal Error Enable/Disable.

SECE

Root PCI Express System Error on Correctable Error Enable/Disable.

PME SCI

PCI Express PME SCI Enable/Disable.

Hot Plug

PCI Express Hot Plug Enable/Disable.

Advanced Error Reporting

Advanced Error Reporting Enable/Disable.

PCIe Speed

Configure PCIe Speed

Transmitter Half Swing

Transmitter Half Swing Enable/Disable.

Detect Timeout

The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.

Extra Bus Reserved

Extra Bus Reserved (0-7) for bridges behind this Root Bridge.

Reserved Memory

Reserved Memory for this Root Bridge (1-20) MB

Reserved I/O

Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge.

PCH PCIe LTR Configuration

LTR

PCH PCIE Latency Reporting Enable/Disable

Snoop Latency Override

Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Snoop Latency Value

LTR Snoop Latency value of PCH PCIE

Snoop Latency Multiplier

LTR Snoop Latency Multiplier of PCH PCIE

Non Snoop Latency Override

Non Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Non Snoop Latency Value

LTR Non Snoop Latency value of PCH PCIE

Non Snoop Latency Multiplier

LTR Non Snoop Latency Multiplier of PCH PCIE

Force LTR Override

Force LTR Override for PCH PCIE. Disabled: LTR override values will not be forced. Enable: LTR override values will be forced and LTR messages from the device will be ignored.

LTR Lock

PCIE LTR Configuration Lock

PCI Express Root Port 14

Control the PCI Express Root Port.

Connection Type

Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.

ASPM

PCI Express Active State Power Management settings.

L1 Substates

PCI Express L1 Substates settings.

ACS

Enable/Disable Access Control Services Extended Capability

PTM

Enable/Disable Precision Time Measurement

DPC

Enable/Disable Downstream Port Containment

EDPC

Enable/Disable Rootport extensions for Downstream Port Containment

URR

PCI Express Unsupported Request Reporting Enable/Disable.

FER

PCI Express Device Fatal Error Reporting Enable/Disable.

NFER

PCI Express Device Non-Fatal Error Reporting Enable/Disable.

CER

PCI Express Device Correctable Error Reporting Enable/Disable.

SEFE

Root PCI Express System Error on Fatal Error Enable/Disable.

SENFE

Root PCI Express System Error on Non-Fatal Error Enable/Disable.

SECE

Root PCI Express System Error on Correctable Error Enable/Disable.

PME SCI

PCI Express PME SCI Enable/Disable.

Hot Plug

PCI Express Hot Plug Enable/Disable.

Advanced Error Reporting

Advanced Error Reporting Enable/Disable.

PCIe Speed

Configure PCIe Speed

Transmitter Half Swing

Transmitter Half Swing Enable/Disable.

Detect Timeout

The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.

Extra Bus Reserved

Extra Bus Reserved (0-7) for bridges behind this Root Bridge.

Reserved Memory

Reserved Memory for this Root Bridge (1-20) MB

Reserved I/O

Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge.

PCH PCIe LTR Configuration

LTR

PCH PCIE Latency Reporting Enable/Disable

Snoop Latency Override

Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Snoop Latency Value

LTR Snoop Latency value of PCH PCIE

Snoop Latency Multiplier

LTR Snoop Latency Multiplier of PCH PCIE

Non Snoop Latency Override

Non Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Non Snoop Latency Value

LTR Non Snoop Latency value of PCH PCIE

Non Snoop Latency Multiplier

LTR Non Snoop Latency Multiplier of PCH PCIE

Force LTR Override

Force LTR Override for PCH PCIE. Disabled: LTR override values will not be forced. Enable: LTR override values will be forced and LTR messages from the device will be ignored.

LTR Lock

PCIE LTR Configuration Lock

PCI Express Root Port 15

Control the PCI Express Root Port.

Connection Type

Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.

ASPM

PCI Express Active State Power Management settings.

L1 Substates

PCI Express L1 Substates settings.

ACS

Enable/Disable Access Control Services Extended Capability

PTM

Enable/Disable Precision Time Measurement

DPC

Enable/Disable Downstream Port Containment

EDPC

Enable/Disable Rootport extensions for Downstream Port Containment

URR

PCI Express Unsupported Request Reporting Enable/Disable.

FER

PCI Express Device Fatal Error Reporting Enable/Disable.

NFER

PCI Express Device Non-Fatal Error Reporting Enable/Disable.

CER

PCI Express Device Correctable Error Reporting Enable/Disable.

SEFE

Root PCI Express System Error on Fatal Error Enable/Disable.

SENFE

Root PCI Express System Error on Non-Fatal Error Enable/Disable.

SECE

Root PCI Express System Error on Correctable Error Enable/Disable.

PME SCI

PCI Express PME SCI Enable/Disable.

Hot Plug

PCI Express Hot Plug Enable/Disable.

Advanced Error Reporting

Advanced Error Reporting Enable/Disable.

PCIe Speed

Configure PCIe Speed

Transmitter Half Swing

Transmitter Half Swing Enable/Disable.

Detect Timeout

The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.

Extra Bus Reserved

Extra Bus Reserved (0-7) for bridges behind this Root Bridge.

Reserved Memory

Reserved Memory for this Root Bridge (1-20) MB

Reserved I/O

Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge.

PCH PCIe LTR Configuration

LTR

PCH PCIE Latency Reporting Enable/Disable

Snoop Latency Override

Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Snoop Latency Value

LTR Snoop Latency value of PCH PCIE

Snoop Latency Multiplier

LTR Snoop Latency Multiplier of PCH PCIE

Non Snoop Latency Override

Non Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Non Snoop Latency Value

LTR Non Snoop Latency value of PCH PCIE

Non Snoop Latency Multiplier

LTR Non Snoop Latency Multiplier of PCH PCIE

Force LTR Override

Force LTR Override for PCH PCIE. Disabled: LTR override values will not be forced. Enable: LTR override values will be forced and LTR messages from the device will be ignored.

LTR Lock

PCIE LTR Configuration Lock

PCI Express Root Port 16

Control the PCI Express Root Port.

Connection Type

Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.

ASPM

PCI Express Active State Power Management settings.

L1 Substates

PCI Express L1 Substates settings.

ACS

Enable/Disable Access Control Services Extended Capability

PTM

Enable/Disable Precision Time Measurement

DPC

Enable/Disable Downstream Port Containment

EDPC

Enable/Disable Rootport extensions for Downstream Port Containment

URR

PCI Express Unsupported Request Reporting Enable/Disable.

FER

PCI Express Device Fatal Error Reporting Enable/Disable.

NFER

PCI Express Device Non-Fatal Error Reporting Enable/Disable.

CER

PCI Express Device Correctable Error Reporting Enable/Disable.

SEFE

Root PCI Express System Error on Fatal Error Enable/Disable.

SENFE

Root PCI Express System Error on Non-Fatal Error Enable/Disable.

SECE

Root PCI Express System Error on Correctable Error Enable/Disable.

PME SCI

PCI Express PME SCI Enable/Disable.

Hot Plug

PCI Express Hot Plug Enable/Disable.

Advanced Error Reporting

Advanced Error Reporting Enable/Disable.

PCIe Speed

Configure PCIe Speed

Transmitter Half Swing

Transmitter Half Swing Enable/Disable.

Detect Timeout

The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.

Extra Bus Reserved

Extra Bus Reserved (0-7) for bridges behind this Root Bridge.

Reserved Memory

Reserved Memory for this Root Bridge (1-20) MB

Reserved I/O

Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge.

PCH PCIe LTR Configuration

LTR

PCH PCIE Latency Reporting Enable/Disable

Snoop Latency Override

Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Snoop Latency Value

LTR Snoop Latency value of PCH PCIE

Snoop Latency Multiplier

LTR Snoop Latency Multiplier of PCH PCIE

Non Snoop Latency Override

Non Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Non Snoop Latency Value

LTR Non Snoop Latency value of PCH PCIE

Non Snoop Latency Multiplier

LTR Non Snoop Latency Multiplier of PCH PCIE

Force LTR Override

Force LTR Override for PCH PCIE. Disabled: LTR override values will not be forced. Enable: LTR override values will be forced and LTR messages from the device will be ignored.

LTR Lock

PCIE LTR Configuration Lock

PCI Express Root Port 17

Control the PCI Express Root Port.

Connection Type

Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.

ASPM

PCI Express Active State Power Management settings.

L1 Substates

PCI Express L1 Substates settings.

ACS

Enable/Disable Access Control Services Extended Capability

PTM

Enable/Disable Precision Time Measurement

DPC

Enable/Disable Downstream Port Containment

EDPC

Enable/Disable Rootport extensions for Downstream Port Containment

URR

PCI Express Unsupported Request Reporting Enable/Disable.

FER

PCI Express Device Fatal Error Reporting Enable/Disable.

NFER

PCI Express Device Non-Fatal Error Reporting Enable/Disable.

CER

PCI Express Device Correctable Error Reporting Enable/Disable.

SEFE

Root PCI Express System Error on Fatal Error Enable/Disable.

SENFE

Root PCI Express System Error on Non-Fatal Error Enable/Disable.

SECE

Root PCI Express System Error on Correctable Error Enable/Disable.

PME SCI

PCI Express PME SCI Enable/Disable.

Hot Plug

PCI Express Hot Plug Enable/Disable.

Advanced Error Reporting

Advanced Error Reporting Enable/Disable.

PCIe Speed

Configure PCIe Speed

Transmitter Half Swing

Transmitter Half Swing Enable/Disable.

Detect Timeout

The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.

Extra Bus Reserved

Extra Bus Reserved (0-7) for bridges behind this Root Bridge.

Reserved Memory

Reserved Memory for this Root Bridge (1-20) MB

Reserved I/O

Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge.

PCH PCIe LTR Configuration

LTR

PCH PCIE Latency Reporting Enable/Disable

Snoop Latency Override

Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Snoop Latency Value

LTR Snoop Latency value of PCH PCIE

Snoop Latency Multiplier

LTR Snoop Latency Multiplier of PCH PCIE

Non Snoop Latency Override

Non Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Non Snoop Latency Value

LTR Non Snoop Latency value of PCH PCIE

Non Snoop Latency Multiplier

LTR Non Snoop Latency Multiplier of PCH PCIE

Force LTR Override

Force LTR Override for PCH PCIE. Disabled: LTR override values will not be forced. Enable: LTR override values will be forced and LTR messages from the device will be ignored.

LTR Lock

PCIE LTR Configuration Lock

PCI Express Root Port 18

Control the PCI Express Root Port.

Connection Type

Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.

ASPM

PCI Express Active State Power Management settings.

L1 Substates

PCI Express L1 Substates settings.

ACS

Enable/Disable Access Control Services Extended Capability

PTM

Enable/Disable Precision Time Measurement

DPC

Enable/Disable Downstream Port Containment

EDPC

Enable/Disable Rootport extensions for Downstream Port Containment

URR

PCI Express Unsupported Request Reporting Enable/Disable.

FER

PCI Express Device Fatal Error Reporting Enable/Disable.

NFER

PCI Express Device Non-Fatal Error Reporting Enable/Disable.

CER

PCI Express Device Correctable Error Reporting Enable/Disable.

SEFE

Root PCI Express System Error on Fatal Error Enable/Disable.

SENFE

Root PCI Express System Error on Non-Fatal Error Enable/Disable.

SECE

Root PCI Express System Error on Correctable Error Enable/Disable.

PME SCI

PCI Express PME SCI Enable/Disable.

Hot Plug

PCI Express Hot Plug Enable/Disable.

Advanced Error Reporting

Advanced Error Reporting Enable/Disable.

PCIe Speed

Configure PCIe Speed

Transmitter Half Swing

Transmitter Half Swing Enable/Disable.

Detect Timeout

The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.

Extra Bus Reserved

Extra Bus Reserved (0-7) for bridges behind this Root Bridge.

Reserved Memory

Reserved Memory for this Root Bridge (1-20) MB

Reserved I/O

Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge.

PCH PCIe LTR Configuration

LTR

PCH PCIE Latency Reporting Enable/Disable

Snoop Latency Override

Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Snoop Latency Value

LTR Snoop Latency value of PCH PCIE

Snoop Latency Multiplier

LTR Snoop Latency Multiplier of PCH PCIE

Non Snoop Latency Override

Non Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Non Snoop Latency Value

LTR Non Snoop Latency value of PCH PCIE

Non Snoop Latency Multiplier

LTR Non Snoop Latency Multiplier of PCH PCIE

Force LTR Override

Force LTR Override for PCH PCIE. Disabled: LTR override values will not be forced. Enable: LTR override values will be forced and LTR messages from the device will be ignored.

LTR Lock

PCIE LTR Configuration Lock

PCI Express Root Port 19

Control the PCI Express Root Port.

Connection Type

Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.

ASPM

PCI Express Active State Power Management settings.

L1 Substates

PCI Express L1 Substates settings.

ACS

Enable/Disable Access Control Services Extended Capability

PTM

Enable/Disable Precision Time Measurement

DPC

Enable/Disable Downstream Port Containment

EDPC

Enable/Disable Rootport extensions for Downstream Port Containment

URR

PCI Express Unsupported Request Reporting Enable/Disable.

FER

PCI Express Device Fatal Error Reporting Enable/Disable.

NFER

PCI Express Device Non-Fatal Error Reporting Enable/Disable.

CER

PCI Express Device Correctable Error Reporting Enable/Disable.

SEFE

Root PCI Express System Error on Fatal Error Enable/Disable.

SENFE

Root PCI Express System Error on Non-Fatal Error Enable/Disable.

SECE

Root PCI Express System Error on Correctable Error Enable/Disable.

PME SCI

PCI Express PME SCI Enable/Disable.

Hot Plug

PCI Express Hot Plug Enable/Disable.

Advanced Error Reporting

Advanced Error Reporting Enable/Disable.

PCIe Speed

Configure PCIe Speed

Transmitter Half Swing

Transmitter Half Swing Enable/Disable.

Detect Timeout

The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.

Extra Bus Reserved

Extra Bus Reserved (0-7) for bridges behind this Root Bridge.

Reserved Memory

Reserved Memory for this Root Bridge (1-20) MB

Reserved I/O

Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge.

PCH PCIe LTR Configuration

LTR

PCH PCIE Latency Reporting Enable/Disable

Snoop Latency Override

Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Snoop Latency Value

LTR Snoop Latency value of PCH PCIE

Snoop Latency Multiplier

LTR Snoop Latency Multiplier of PCH PCIE

Non Snoop Latency Override

Non Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Non Snoop Latency Value

LTR Non Snoop Latency value of PCH PCIE

Non Snoop Latency Multiplier

LTR Non Snoop Latency Multiplier of PCH PCIE

Force LTR Override

Force LTR Override for PCH PCIE. Disabled: LTR override values will not be forced. Enable: LTR override values will be forced and LTR messages from the device will be ignored.

LTR Lock

PCIE LTR Configuration Lock

PCI Express Root Port 20

Control the PCI Express Root Port.

Connection Type

Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.

ASPM

PCI Express Active State Power Management settings.

L1 Substates

PCI Express L1 Substates settings.

ACS

Enable/Disable Access Control Services Extended Capability

PTM

Enable/Disable Precision Time Measurement

DPC

Enable/Disable Downstream Port Containment

EDPC

Enable/Disable Rootport extensions for Downstream Port Containment

URR

PCI Express Unsupported Request Reporting Enable/Disable.

FER

PCI Express Device Fatal Error Reporting Enable/Disable.

NFER

PCI Express Device Non-Fatal Error Reporting Enable/Disable.

CER

PCI Express Device Correctable Error Reporting Enable/Disable.

SEFE

Root PCI Express System Error on Fatal Error Enable/Disable.

SENFE

Root PCI Express System Error on Non-Fatal Error Enable/Disable.

SECE

Root PCI Express System Error on Correctable Error Enable/Disable.

PME SCI

PCI Express PME SCI Enable/Disable.

Hot Plug

PCI Express Hot Plug Enable/Disable.

Advanced Error Reporting

Advanced Error Reporting Enable/Disable.

PCIe Speed

Configure PCIe Speed

Transmitter Half Swing

Transmitter Half Swing Enable/Disable.

Detect Timeout

The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.

Extra Bus Reserved

Extra Bus Reserved (0-7) for bridges behind this Root Bridge.

Reserved Memory

Reserved Memory for this Root Bridge (1-20) MB

Reserved I/O

Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge.

PCH PCIe LTR Configuration

LTR

PCH PCIE Latency Reporting Enable/Disable

Snoop Latency Override

Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Snoop Latency Value

LTR Snoop Latency value of PCH PCIE

Snoop Latency Multiplier

LTR Snoop Latency Multiplier of PCH PCIE

Non Snoop Latency Override

Non Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Non Snoop Latency Value

LTR Non Snoop Latency value of PCH PCIE

Non Snoop Latency Multiplier

LTR Non Snoop Latency Multiplier of PCH PCIE

Force LTR Override

Force LTR Override for PCH PCIE. Disabled: LTR override values will not be forced. Enable: LTR override values will be forced and LTR messages from the device will be ignored.

LTR Lock

PCIE LTR Configuration Lock

PCI Express Root Port 21

Control the PCI Express Root Port.

Connection Type

Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.

ASPM

PCI Express Active State Power Management settings.

L1 Substates

PCI Express L1 Substates settings.

ACS

Enable/Disable Access Control Services Extended Capability

PTM

Enable/Disable Precision Time Measurement

DPC

Enable/Disable Downstream Port Containment

EDPC

Enable/Disable Rootport extensions for Downstream Port Containment

URR

PCI Express Unsupported Request Reporting Enable/Disable.

FER

PCI Express Device Fatal Error Reporting Enable/Disable.

NFER

PCI Express Device Non-Fatal Error Reporting Enable/Disable.

CER

PCI Express Device Correctable Error Reporting Enable/Disable.

SEFE

Root PCI Express System Error on Fatal Error Enable/Disable.

SENFE

Root PCI Express System Error on Non-Fatal Error Enable/Disable.

SECE

Root PCI Express System Error on Correctable Error Enable/Disable.

PME SCI

PCI Express PME SCI Enable/Disable.

Hot Plug

PCI Express Hot Plug Enable/Disable.

Advanced Error Reporting

Advanced Error Reporting Enable/Disable.

PCIe Speed

Configure PCIe Speed

Transmitter Half Swing

Transmitter Half Swing Enable/Disable.

Detect Timeout

The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.

Extra Bus Reserved

Extra Bus Reserved (0-7) for bridges behind this Root Bridge.

Reserved Memory

Reserved Memory for this Root Bridge (1-20) MB

Reserved I/O

Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge.

PCH PCIe LTR Configuration

LTR

PCH PCIE Latency Reporting Enable/Disable

Snoop Latency Override

Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Snoop Latency Value

LTR Snoop Latency value of PCH PCIE

Snoop Latency Multiplier

LTR Snoop Latency Multiplier of PCH PCIE

Non Snoop Latency Override

Non Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Non Snoop Latency Value

LTR Non Snoop Latency value of PCH PCIE

Non Snoop Latency Multiplier

LTR Non Snoop Latency Multiplier of PCH PCIE

Force LTR Override

Force LTR Override for PCH PCIE. Disabled: LTR override values will not be forced. Enable: LTR override values will be forced and LTR messages from the device will be ignored.

LTR Lock

PCIE LTR Configuration Lock

PCI Express Root Port 22

Control the PCI Express Root Port.

Connection Type

Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.

ASPM

PCI Express Active State Power Management settings.

L1 Substates

PCI Express L1 Substates settings.

ACS

Enable/Disable Access Control Services Extended Capability

PTM

Enable/Disable Precision Time Measurement

DPC

Enable/Disable Downstream Port Containment

EDPC

Enable/Disable Rootport extensions for Downstream Port Containment

URR

PCI Express Unsupported Request Reporting Enable/Disable.

FER

PCI Express Device Fatal Error Reporting Enable/Disable.

NFER

PCI Express Device Non-Fatal Error Reporting Enable/Disable.

CER

PCI Express Device Correctable Error Reporting Enable/Disable.

SEFE

Root PCI Express System Error on Fatal Error Enable/Disable.

SENFE

Root PCI Express System Error on Non-Fatal Error Enable/Disable.

SECE

Root PCI Express System Error on Correctable Error Enable/Disable.

PME SCI

PCI Express PME SCI Enable/Disable.

Hot Plug

PCI Express Hot Plug Enable/Disable.

Advanced Error Reporting

Advanced Error Reporting Enable/Disable.

PCIe Speed

Configure PCIe Speed

Transmitter Half Swing

Transmitter Half Swing Enable/Disable.

Detect Timeout

The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.

Extra Bus Reserved

Extra Bus Reserved (0-7) for bridges behind this Root Bridge.

Reserved Memory

Reserved Memory for this Root Bridge (1-20) MB

Reserved I/O

Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge.

PCH PCIe LTR Configuration

LTR

PCH PCIE Latency Reporting Enable/Disable

Snoop Latency Override

Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Snoop Latency Value

LTR Snoop Latency value of PCH PCIE

Snoop Latency Multiplier

LTR Snoop Latency Multiplier of PCH PCIE

Non Snoop Latency Override

Non Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Non Snoop Latency Value

LTR Non Snoop Latency value of PCH PCIE

Non Snoop Latency Multiplier

LTR Non Snoop Latency Multiplier of PCH PCIE

Force LTR Override

Force LTR Override for PCH PCIE. Disabled: LTR override values will not be forced. Enable: LTR override values will be forced and LTR messages from the device will be ignored.

LTR Lock

PCIE LTR Configuration Lock

PCI Express Root Port 23

Control the PCI Express Root Port.

Connection Type

Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.

ASPM

PCI Express Active State Power Management settings.

L1 Substates

PCI Express L1 Substates settings.

ACS

Enable/Disable Access Control Services Extended Capability

PTM

Enable/Disable Precision Time Measurement

DPC

Enable/Disable Downstream Port Containment

EDPC

Enable/Disable Rootport extensions for Downstream Port Containment

URR

PCI Express Unsupported Request Reporting Enable/Disable.

FER

PCI Express Device Fatal Error Reporting Enable/Disable.

NFER

PCI Express Device Non-Fatal Error Reporting Enable/Disable.

CER

PCI Express Device Correctable Error Reporting Enable/Disable.

SEFE

Root PCI Express System Error on Fatal Error Enable/Disable.

SENFE

Root PCI Express System Error on Non-Fatal Error Enable/Disable.

SECE

Root PCI Express System Error on Correctable Error Enable/Disable.

PME SCI

PCI Express PME SCI Enable/Disable.

Hot Plug

PCI Express Hot Plug Enable/Disable.

Advanced Error Reporting

Advanced Error Reporting Enable/Disable.

PCIe Speed

Configure PCIe Speed

Transmitter Half Swing

Transmitter Half Swing Enable/Disable.

Detect Timeout

The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.

Extra Bus Reserved

Extra Bus Reserved (0-7) for bridges behind this Root Bridge.

Reserved Memory

Reserved Memory for this Root Bridge (1-20) MB

Reserved I/O

Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge.

PCH PCIe LTR Configuration

LTR

PCH PCIE Latency Reporting Enable/Disable

Snoop Latency Override

Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Snoop Latency Value

LTR Snoop Latency value of PCH PCIE

Snoop Latency Multiplier

LTR Snoop Latency Multiplier of PCH PCIE

Non Snoop Latency Override

Non Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Non Snoop Latency Value

LTR Non Snoop Latency value of PCH PCIE

Non Snoop Latency Multiplier

LTR Non Snoop Latency Multiplier of PCH PCIE

Force LTR Override

Force LTR Override for PCH PCIE. Disabled: LTR override values will not be forced. Enable: LTR override values will be forced and LTR messages from the device will be ignored.

LTR Lock

PCIE LTR Configuration Lock

PCI Express Root Port 24

Control the PCI Express Root Port.

Connection Type

Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.

ASPM

PCI Express Active State Power Management settings.

L1 Substates

PCI Express L1 Substates settings.

ACS

Enable/Disable Access Control Services Extended Capability

PTM

Enable/Disable Precision Time Measurement

DPC

Enable/Disable Downstream Port Containment

EDPC

Enable/Disable Rootport extensions for Downstream Port Containment

URR

PCI Express Unsupported Request Reporting Enable/Disable.

FER

PCI Express Device Fatal Error Reporting Enable/Disable.

NFER

PCI Express Device Non-Fatal Error Reporting Enable/Disable.

CER

PCI Express Device Correctable Error Reporting Enable/Disable.

SEFE

Root PCI Express System Error on Fatal Error Enable/Disable.

SENFE

Root PCI Express System Error on Non-Fatal Error Enable/Disable.

SECE

Root PCI Express System Error on Correctable Error Enable/Disable.

PME SCI

PCI Express PME SCI Enable/Disable.

Hot Plug

PCI Express Hot Plug Enable/Disable.

Advanced Error Reporting

Advanced Error Reporting Enable/Disable.

PCIe Speed

Configure PCIe Speed

Transmitter Half Swing

Transmitter Half Swing Enable/Disable.

Detect Timeout

The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.

Extra Bus Reserved

Extra Bus Reserved (0-7) for bridges behind this Root Bridge.

Reserved Memory

Reserved Memory for this Root Bridge (1-20) MB

Reserved I/O

Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge.

PCH PCIe LTR Configuration

LTR

PCH PCIE Latency Reporting Enable/Disable

Snoop Latency Override

Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Snoop Latency Value

LTR Snoop Latency value of PCH PCIE

Snoop Latency Multiplier

LTR Snoop Latency Multiplier of PCH PCIE

Non Snoop Latency Override

Non Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.

Non Snoop Latency Value

LTR Non Snoop Latency value of PCH PCIE

Non Snoop Latency Multiplier

LTR Non Snoop Latency Multiplier of PCH PCIE

Force LTR Override

Force LTR Override for PCH PCIE. Disabled: LTR override values will not be forced. Enable: LTR override values will be forced and LTR messages from the device will be ignored.

LTR Lock

PCIE LTR Configuration Lock

Clock0 assignment

Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.

ClkReq for Clock0

Platform-POR = CLKREQ signal is assigned to CLKSRC according to board layout. Disabled = CLKREQ will not be used.

Clock1 assignment

Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.

ClkReq for Clock1

Platform-POR = CLKREQ signal is assigned to CLKSRC according to board layout. Disabled = CLKREQ will not be used.

Clock2 assignment

Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.

ClkReq for Clock2

Platform-POR = CLKREQ signal is assigned to CLKSRC according to board layout. Disabled = CLKREQ will not be used.

Clock3 assignment

Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.

ClkReq for Clock3

Platform-POR = CLKREQ signal is assigned to CLKSRC according to board layout. Disabled = CLKREQ will not be used.

Clock4 assignment

Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.

ClkReq for Clock4

Platform-POR = CLKREQ signal is assigned to CLKSRC according to board layout. Disabled = CLKREQ will not be used.

Clock5 assignment

Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.

ClkReq for Clock5

Platform-POR = CLKREQ signal is assigned to CLKSRC according to board layout. Disabled = CLKREQ will not be used.

Clock6 assignment

Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.

ClkReq for Clock6

Platform-POR = CLKREQ signal is assigned to CLKSRC according to board layout. Disabled = CLKREQ will not be used.

Clock7 assignment

Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.

ClkReq for Clock7

Platform-POR = CLKREQ signal is assigned to CLKSRC according to board layout. Disabled = CLKREQ will not be used.

Clock8 assignment

Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.

ClkReq for Clock8

Platform-POR = CLKREQ signal is assigned to CLKSRC according to board layout. Disabled = CLKREQ will not be used.

Clock9 assignment

Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.

ClkReq for Clock9

Platform-POR = CLKREQ signal is assigned to CLKSRC according to board layout. Disabled = CLKREQ will not be used.

Clock10 assignment

Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.

ClkReq for Clock10

Platform-POR = CLKREQ signal is assigned to CLKSRC according to board layout. Disabled = CLKREQ will not be used.

Clock11 assignment

Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.

ClkReq for Clock11

Platform-POR = CLKREQ signal is assigned to CLKSRC according to board layout. Disabled = CLKREQ will not be used.

Clock12 assignment

Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.

ClkReq for Clock12

Platform-POR = CLKREQ signal is assigned to CLKSRC according to board layout. Disabled = CLKREQ will not be used.

Clock13 assignment

Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.

ClkReq for Clock13

Platform-POR = CLKREQ signal is assigned to CLKSRC according to board layout. Disabled = CLKREQ will not be used.

Clock14 assignment

Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.

ClkReq for Clock14

Platform-POR = CLKREQ signal is assigned to CLKSRC according to board layout. Disabled = CLKREQ will not be used.

Clock15 assignment

Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.

ClkReq for Clock15

Platform-POR = CLKREQ signal is assigned to CLKSRC according to board layout. Disabled = CLKREQ will not be used.

Touch Host Controller Configuration Settings

THC Port Configuration

Assign Port to THC

Port Clock

SPI_DFX_CLK_EN BIT set to 0 or 1

THC Port Configuration

Assign Port to THC

Port Clock

SPI_DFX_CLK_EN BIT set to 0 or 1

THC is not available

HD Audio Subsystem Configuration Settings

HD Audio

Control Detection of the HD-Audio device. Disabled = HDA will be unconditionally disabled Enabled = HDA will be unconditionally enabled.

Audio DSP

Enable/Disable Audio DSP.

Audio DSP Compliance Mode

Specifies DSP enabled system compliance: 1. Non-UAA (IntelSST driver support only - CC_040100) 2. UAA (HD Audio Inbox or IntelSST driver support - CC_040380) Note: NHLT (DMIC/BT/I2S configuration) is published for non-UAA only.

HDA Link Enabled

Muxed interfaces: 1) HDA/SSP0 2) HDA[SDI1]/SSP1 3) DMIC0/SNDW4 4) DMIC1/SNDW3 CNL only: 5) HDA/SNDW1 6) SSP1/SNDW2

DMIC #0 Enabled

Muxed interfaces: 1) HDA/SSP0 2) HDA[SDI1]/SSP1 3) DMIC0/SNDW4 4) DMIC1/SNDW3 CNL only: 5) HDA/SNDW1 6) SSP1/SNDW2

Dmic Clock Source Select

N/A

DMIC #1 Enabled

Muxed interfaces: 1) HDA/SSP0 2) HDA[SDI1]/SSP1 3) DMIC0/SNDW4 4) DMIC1/SNDW3 CNL only: 5) HDA/SNDW1 6) SSP1/SNDW2

Dmic Clock Source Select

N/A

SSP #0 Enabled

Muxed interfaces: 1) HDA/SSP0 2) HDA[SDI1]/SSP1 3) DMIC0/SNDW4 4) DMIC1/SNDW3 CNL only: 5) HDA/SNDW1 6) SSP1/SNDW2

SSP #1 Enabled

Muxed interfaces: 1) HDA/SSP0 2) HDA[SDI1]/SSP1 3) DMIC0/SNDW4 4) DMIC1/SNDW3 CNL only: 5) HDA/SNDW1 6) SSP1/SNDW2

SSP #2 Enabled

Muxed interfaces: 1) HDA/SSP0 2) HDA[SDI1]/SSP1 3) DMIC0/SNDW4 4) DMIC1/SNDW3 CNL only: 5) HDA/SNDW1 6) SSP1/SNDW2

SSP #3 Enabled

Muxed interfaces: 1) HDA/SSP0 2) HDA[SDI1]/SSP1 3) DMIC0/SNDW4 4) DMIC1/SNDW3 CNL only: 5) HDA/SNDW1 6) SSP1/SNDW2

SSP #4 Enabled

Muxed interfaces: 1) HDA/SSP0 2) HDA[SDI1]/SSP1 3) DMIC0/SNDW4 4) DMIC1/SNDW3 CNL only: 5) HDA/SNDW1 6) SSP1/SNDW2

SSP #5 Enabled

Muxed interfaces: 1) HDA/SSP0 2) HDA[SDI1]/SSP1 3) DMIC0/SNDW4 4) DMIC1/SNDW3 CNL only: 5) HDA/SNDW1 6) SSP1/SNDW2

SNDW #1 Enabled

Muxed interfaces: 1) HDA/SSP0 2) HDA[SDI1]/SSP1 3) DMIC0/SNDW4 4) DMIC1/SNDW3 CNL only: 5) HDA/SNDW1 6) SSP1/SNDW2

SNDW #2 Enabled

Muxed interfaces: 1) HDA/SSP0 2) HDA[SDI1]/SSP1 3) DMIC0/SNDW4 4) DMIC1/SNDW3 CNL only: 5) HDA/SNDW1 6) SSP1/SNDW2

SNDW #3 Enabled

Muxed interfaces: 1) HDA/SSP0 2) HDA[SDI1]/SSP1 3) DMIC0/SNDW4 4) DMIC1/SNDW3 CNL only: 5) HDA/SNDW1 6) SSP1/SNDW2

SNDW #4 Enabled

Muxed interfaces: 1) HDA/SSP0 2) HDA[SDI1]/SSP1 3) DMIC0/SNDW4 4) DMIC1/SNDW3 CNL only: 5) HDA/SNDW1 6) SSP1/SNDW2

HDA-Link Codec Select

Selects whether Platform Onboard Codec (single Verb Table installed) or External Codec Kit (multiple Verb Tables installed) will be used.

HD Audio Advanced Configuration

HD Audio DSP Features Configuration

HD Audio Subsystem Advanced Configuration Settings

iDisplay Audio Disconnect

Disconnects SDI2 signal to hide/disable iDisplay Audio Codec.

Codec Sx Wake Capability

Capability to detect wake initiated by a codec in Sx (eg by modem codec)

PME Enable

Enables PME wake of HD Audio controller during POST.

Statically Switchable BCLK Clock Frequency Configuration:

HD Audio Link Frequency

Selects HD Audio Link frequency. Applicable only if HDA codec supports selected frequency.

iDisplay Audio Link Frequency

Selects iDisplay Link frequency.

iDisplay Audio Link T-Mode

Indicates whether SDI is operating in 1T, 2T (CNL) or 2T, 4T, 8T mode (ICL).

Autonomous Clock Stop SNDW #1

Enable/Disable Autonomous Clock Stop for SoundWire LINK1

Autonomous Clock Stop SNDW #2

Enable/Disable Autonomous Clock Stop for SoundWire LINK2

Autonomous Clock Stop SNDW #3

Enable/Disable Autonomous Clock Stop for SoundWire LINK3

Autonomous Clock Stop SNDW #4

Enable/Disable Autonomous Clock Stop for SoundWire LINK4

Data On Active Interval Select SNDW #1

Data On Active Interval Select: 1) 3 clock periods 2) 4 clock periods 3) 5 clock periods 4) 6 clock periods 5)

Data On Active Interval Select SNDW #2

Data On Active Interval Select: 1) 3 clock periods 2) 4 clock periods 3) 5 clock periods 4) 6 clock periods 5)

Data On Active Interval Select SNDW #3

Data On Active Interval Select: 1) 3 clock periods 2) 4 clock periods 3) 5 clock periods 4) 6 clock periods 5)

Data On Active Interval Select SNDW #4

Data On Active Interval Select: 1) 3 clock periods 2) 4 clock periods 3) 5 clock periods 4) 6 clock periods 5)

Data On Delay Select SNDW #1

Data On Delay Select: 1) 2 clock periods 2) 3 clock periods 3)

Data On Delay Select SNDW #2

Data On Delay Select: 1) 2 clock periods 2) 3 clock periods 3)

Data On Delay Select SNDW #3

Data On Delay Select: 1) 2 clock periods 2) 3 clock periods 3)

Data On Delay Select SNDW #4

Data On Delay Select: 1) 2 clock periods 2) 3 clock periods 3)

HD Audio Subsystem Features Configuration (ACPI)

Audio DSP NHLT Endpoints Configuration:

NHLT External Table

Load external NHLT table from binary file instead of using NHLT built from policy setting.

DMIC

Selects DMIC to expose in NHLT ACPI table

Bluetooth

Enables/Disables Bluetooth Endpoint in NHLT ACPI table

I2S

Enables/Disables I2S Endpoint in NHLT ACPI table.

I2S Codec Select

Selects I2S Audio Codec support. Note: SerialIo UART0 must be disabled to enable external I2S codec (due to GPIO pin muxing).

Audio DSP Feature Support:

WoV (Wake on Voice) Enabled

Enables/Disables DSP Feature. Bitmask structure: [BIT0] - WoV [BIT1] - BT Sideband [BIT2] - Codec based VAD [BIT5] - BT Intel HFP [BIT6] - BT Intel A2DP [BIT7] - DSP based speech pre-processing disabled (for Intel WoV mode) [BIT8] - WoV Mode: Intel WoV / Windows Voice Activation for Cortana

Bluetooth Sideband Enabled

BT Intel HFP Enabled

BT Intel A2DP Enabled

Codec based VAD Enabled

DSP based Speech Pre-Processing Disabled Enabled

Voice Activity Detection

Audio DSP Pre/Post-Processing Module Support:

Waves Post-process Enabled

Enables/Disables 3rd Party Processing Module Support (identified by GUID). WoV must be enabled as a feature first to select relevant WoV IP.

DTS Enabled

Enables/Disables 3rd Party Processing Module Support (identified by GUID). WoV must be enabled as a feature first to select relevant WoV IP.

IntelSST Speech Enabled

Enables/Disables 3rd Party Processing Module Support (identified by GUID). WoV must be enabled as a feature first to select relevant WoV IP.

Dolby Enabled

Enables/Disables 3rd Party Processing Module Support (identified by GUID). WoV must be enabled as a feature first to select relevant WoV IP.

Waves Pre-process Enabled

Enables/Disables 3rd Party Processing Module Support (identified by GUID). WoV must be enabled as a feature first to select relevant WoV IP.

Audyssey Enabled

Enables/Disables 3rd Party Processing Module Support (identified by GUID). WoV must be enabled as a feature first to select relevant WoV IP.

Maxim Smart AMP Enabled

Enables/Disables 3rd Party Processing Module Support (identified by GUID). WoV must be enabled as a feature first to select relevant WoV IP.

ForteMedia SAMSoft Enabled

Enables/Disables 3rd Party Processing Module Support (identified by GUID). WoV must be enabled as a feature first to select relevant WoV IP.

Sound Research IP Enabled

Enables/Disables 3rd Party Processing Module Support (identified by GUID). WoV must be enabled as a feature first to select relevant WoV IP.

Conexant Pre-Process Enabled

Enables/Disables 3rd Party Processing Module Support (identified by GUID). WoV must be enabled as a feature first to select relevant WoV IP.

Conexant Smart Amp Enabled

Enables/Disables 3rd Party Processing Module Support (identified by GUID). WoV must be enabled as a feature first to select relevant WoV IP.

Realtek Post-Process Enabled

Enables/Disables 3rd Party Processing Module Support (identified by GUID). WoV must be enabled as a feature first to select relevant WoV IP.

Realtek Smart Amp Enabled

Enables/Disables 3rd Party Processing Module Support (identified by GUID). WoV must be enabled as a feature first to select relevant WoV IP.

Icepower IP MFX sub module Enabled

Enables/Disables 3rd Party Processing Module Support (identified by GUID). WoV must be enabled as a feature first to select relevant WoV IP.

Icepower IP EFX sub module Enabled

Enables/Disables 3rd Party Processing Module Support (identified by GUID). WoV must be enabled as a feature first to select relevant WoV IP.

Icepower IP SFX sub module Enabled

Enables/Disables 3rd Party Processing Module Support (identified by GUID). WoV must be enabled as a feature first to select relevant WoV IP.

Voice Preprocessing Enabled

Enables/Disables 3rd Party Processing Module Support (identified by GUID). WoV must be enabled as a feature first to select relevant WoV IP.

Custom Module 'Alpha' Enabled

Enables/Disables 3rd Party Processing Module Support (identified by GUID). WoV must be enabled as a feature first to select relevant WoV IP.

'Alpha' GUID:

Input hex digit character in aabbccdd-eeff-gghh-iijj-kkllmmnnoopp format.

Custom Module 'Beta' Enabled

Enables/Disables 3rd Party Processing Module Support (identified by GUID). WoV must be enabled as a feature first to select relevant WoV IP.

'Beta' GUID:

Input hex digit character in aabbccdd-eeff-gghh-iijj-kkllmmnnoopp format.

Custom Module 'Gamma' Enabled

Enables/Disables 3rd Party Processing Module Support (identified by GUID). WoV must be enabled as a feature first to select relevant WoV IP.

'Gamma' GUID:

Input hex digit character in aabbccdd-eeff-gghh-iijj-kkllmmnnoopp format.

Security Configuration

RTC Memory Lock

Enable will lock bytes 38h-3Fh in the lower/upper 128-byte bank of RTC RAM

BIOS Lock

Enable/Disable the PCH BIOS Lock Enable feature. Required to be enabled to ensure SMM protection of flash.

Force unlock on all GPIO pads

If Enabled BIOS will force all GPIO pads to be in unlocked state

SerialIo Configuration

I2C0 Controller

I2C1 Controller

I2C2 Controller

I2C3 Controller

I2C4 Controller

Enables/Disables SerialIo Controller For I2C5 and UART2 to work this device has to be enabled

I2C5 Controller

Enables/Disables SerialIo Controller For this device to work I2C4 has to be enabled

I2C6 Controller

I2C7 Controller

SPI0 Controller

SPI1 Controller

SPI2 Controller

Enables/Disables SerialIo SPI2 Controller The following device depends from: Thermal Subsystem in PCI mode Otherwise SPI2 will not appear in the OS

SPI3 Controller

SPI4 Controller

SPI5 Controller

SPI6 Controller

UART0 Controller

UART1 Controller

UART2 Controller

Set UART2 mode - DBG used for BIOS log print and/or Kernel OS Debug - COM - 16550 compatible serial port with Power Gating support

UART3 Controller

UART4 Controller

UART5 Controller

UART6 Controller

UART2 Controller used as debug port

GPIO IRQ Route

Route all GPIOs to one of the IRQ.

Serial IO I2C0 Settings

Serial IO I2C1 Settings

Serial IO I2C2 Settings

Serial IO I2C3 Settings

Serial IO I2C4 Settings

Serial IO I2C5 Settings

Serial IO SPI0 Settings

Serial IO SPI1 Settings

Serial IO SPI2 Settings

Serial IO UART0 Settings

Serial IO UART1 Settings

Serial IO UART2 Settings

WITT/MITT Test Device

Choose if WITT Device is used and with which controller

WITT/MITT Device selection

Change WITT Device version

UART Test Device

Choose if UART Test Device is used and with which controller

Additional Serial IO devices Enabled

When enabled, ACPI will report additional devices connected to Serial IO.

SerialIO timing parameters Enabled

Enables additional timing parameters for all SeraialIO controllers. Defaults can be changed in each controller setting. Platform restart required to apply changes

Serial IO I2C0 Settings

Connected device

Indicates what type of device is connected to this SerialIo controller

Serial IO Touch Pad Settings

Serial IO Touch Panel Settings

Timing parameters

StandardSpeed SCL High

Default: 612 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

StandardSpeed SCL Low

Default: 706 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

StandardSpeed SDA Hold

Default: 30 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

FastSpeed SCL High

Default: 110 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

FastSpeed SCL Low

Default: 207 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

FastSpeed SDA Hold

Default: 30 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

FastSpeedPlus SCL High

Default: 43 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

FastSpeedPlus SCL Low

Default: 76 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

FastSpeedPlus SDA Hold

Default: 30 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

HighSpeed SCL High

Default: 11 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

HighSpeed SCL Low

Default: 22 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

HighSpeed SDA Hold

Default: 8 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

D0->D3 idle timeout (screen off)

Default: 200 [DEC] Minimum: 1 [DEC] Maximum: 10000 [DEC]

D0->D3 idle timeout (screen on)

Default: 2000 [DEC] Minimum: 1 [DEC] Maximum: 10000 [DEC]

Timing parameters disabled

Serial IO I2C1 Settings

Connected device

Indicates what type of device is connected to this SerialIo controller

Serial IO Touch Pad Settings

Serial IO Touch Panel Settings

Timing parameters

StandardSpeed SCL High

Default: 612 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

StandardSpeed SCL Low

Default: 706 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

StandardSpeed SDA Hold

Default: 30 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

FastSpeed SCL High

Default: 110 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

FastSpeed SCL Low

Default: 207 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

FastSpeed SDA Hold

Default: 30 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

FastSpeedPlus SCL High

Default: 43 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

FastSpeedPlus SCL Low

Default: 76 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

FastSpeedPlus SDA Hold

Default: 30 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

HighSpeed SCL High

Default: 11 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

HighSpeed SCL Low

Default: 22 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

HighSpeed SDA Hold

Default: 8 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

D0->D3 idle timeout (screen off)

Default: 200 [DEC] Minimum: 1 [DEC] Maximum: 10000 [DEC]

D0->D3 idle timeout (screen on)

Default: 2000 [DEC] Minimum: 1 [DEC] Maximum: 10000 [DEC]

Timing parameters disabled

Serial IO I2C2 Settings

Connected device

Indicates what type of device is connected to this SerialIo controller

Serial IO Touch Pad Settings

Serial IO Touch Panel Settings

Timing parameters

StandardSpeed SCL High

Default: 612 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

StandardSpeed SCL Low

Default: 706 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

StandardSpeed SDA Hold

Default: 30 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

FastSpeed SCL High

Default: 110 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

FastSpeed SCL Low

Default: 207 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

FastSpeed SDA Hold

Default: 30 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

FastSpeedPlus SCL High

Default: 43 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

FastSpeedPlus SCL Low

Default: 76 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

FastSpeedPlus SDA Hold

Default: 30 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

HighSpeed SCL High

Default: 11 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

HighSpeed SCL Low

Default: 22 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

HighSpeed SDA Hold

Default: 8 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

D0->D3 idle timeout (screen off)

Default: 200 [DEC] Minimum: 1 [DEC] Maximum: 10000 [DEC]

D0->D3 idle timeout (screen on)

Default: 2000 [DEC] Minimum: 1 [DEC] Maximum: 10000 [DEC]

Timing parameters disabled

Serial IO I2C3 Settings

Connected device

Indicates what type of device is connected to this SerialIo controller

Serial IO Touch Pad Settings

Serial IO Touch Panel Settings

Timing parameters

StandardSpeed SCL High

Default: 612 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

StandardSpeed SCL Low

Default: 706 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

StandardSpeed SDA Hold

Default: 30 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

FastSpeed SCL High

Default: 110 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

FastSpeed SCL Low

Default: 207 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

FastSpeed SDA Hold

Default: 30 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

FastSpeedPlus SCL High

Default: 43 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

FastSpeedPlus SCL Low

Default: 76 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

FastSpeedPlus SDA Hold

Default: 30 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

HighSpeed SCL High

Default: 11 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

HighSpeed SCL Low

Default: 22 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

HighSpeed SDA Hold

Default: 8 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

D0->D3 idle timeout (screen off)

Default: 200 [DEC] Minimum: 1 [DEC] Maximum: 10000 [DEC]

D0->D3 idle timeout (screen on)

Default: 2000 [DEC] Minimum: 1 [DEC] Maximum: 10000 [DEC]

Timing parameters disabled

Serial IO I2C4 Settings

Timing parameters

StandardSpeed SCL High

Default: 612 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

StandardSpeed SCL Low

Default: 706 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

StandardSpeed SDA Hold

Default: 30 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

FastSpeed SCL High

Default: 110 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

FastSpeed SCL Low

Default: 207 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

FastSpeed SDA Hold

Default: 30 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

FastSpeedPlus SCL High

Default: 43 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

FastSpeedPlus SCL Low

Default: 76 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

FastSpeedPlus SDA Hold

Default: 30 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

HighSpeed SCL High

Default: 11 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

HighSpeed SCL Low

Default: 22 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

HighSpeed SDA Hold

Default: 8 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

D0->D3 idle timeout (screen off)

Default: 200 [DEC] Minimum: 1 [DEC] Maximum: 10000 [DEC]

D0->D3 idle timeout (screen on)

Default: 2000 [DEC] Minimum: 1 [DEC] Maximum: 10000 [DEC]

Timing parameters disabled

Serial IO I2C5 Settings

Timing parameters

StandardSpeed SCL High

Default: 612 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

StandardSpeed SCL Low

Default: 706 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

StandardSpeed SDA Hold

Default: 30 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

FastSpeed SCL High

Default: 110 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

FastSpeed SCL Low

Default: 207 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

FastSpeed SDA Hold

Default: 30 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

FastSpeedPlus SCL High

Default: 43 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

FastSpeedPlus SCL Low

Default: 76 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

FastSpeedPlus SDA Hold

Default: 30 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

HighSpeed SCL High

Default: 11 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

HighSpeed SCL Low

Default: 22 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

HighSpeed SDA Hold

Default: 8 [DEC] Minimum: 1 [DEC] Maximum: 65535 [DEC]

D0->D3 idle timeout (screen off)

Default: 200 [DEC] Minimum: 1 [DEC] Maximum: 10000 [DEC]

D0->D3 idle timeout (screen on)

Default: 2000 [DEC] Minimum: 1 [DEC] Maximum: 10000 [DEC]

Timing parameters disabled

Serial IO SPI0 Settings

ChipSelect 0 polarity

Sets initial polarity for ChipSelect signal

ChipSelect 1 polarity

Sets initial polarity for ChipSelect signal

Timing parameters

D0->D3 idle timeout (screen off)

Default: 200 [DEC] Minimum: 1 [DEC] Maximum: 10000 [DEC]

D0->D3 idle timeout (screen on)

Default: 2000 [DEC] Minimum: 1 [DEC] Maximum: 10000 [DEC]

Timing parameters disabled

Serial IO SPI1 Settings

ChipSelect 0 polarity

Sets initial polarity for ChipSelect signal

ChipSelect 1 polarity

Sets initial polarity for ChipSelect signal

Connected device

Indicates what type of device is connected to this SerialIo controller

Serial IO Finger Print Settings

Serial IO SPI2 Settings

ChipSelect 0 polarity

Sets initial polarity for ChipSelect signal

ChipSelect 1 polarity

Sets initial polarity for ChipSelect signal

Connected device

Indicates what type of device is connected to this SerialIo controller

Serial IO Finger Print Settings

Serial IO UART0 Settings

Hardware Flow Control

When enabled configures additional 2 GPIO pads for use as RTS/CTS signals for UART

DMA Enable

Enabled: UART OS driver will use DMA when possible. Disabled: OS driver will enforce PIO mode

Power Gating

Disabled: No _PS0 _PS3 support, device is left in D0, after initialization Enabled: _PS0 _PS3 that supports getting device out of reset Auto: _PS0 and _PS3 detection through ACPI if device was initialized prior to first PG. If it was used (DBG2) PG is disabled

Timing parameters

D0->D3 idle timeout (screen off)

Default: 200 [DEC] Minimum: 1 [DEC] Maximum: 10000 [DEC]

D0->D3 idle timeout (screen on)

Default: 200 [DEC] Minimum: 1 [DEC] Maximum: 10000 [DEC]

Timing parameters disabled

Serial IO UART1 Settings

Hardware Flow Control

When enabled configures additional 2 GPIO pads for use as RTS/CTS signals for UART

DMA Enable

Enabled: UART OS driver will use DMA when possible. Disabled: OS driver will enforce PIO mode

Power Gating

Timing parameters

D0->D3 idle timeout (screen off)

Default: 200 [DEC] Minimum: 1 [DEC] Maximum: 10000 [DEC]

D0->D3 idle timeout (screen on)

Default: 200 [DEC] Minimum: 1 [DEC] Maximum: 10000 [DEC]

Timing parameters disabled

Serial IO UART2 Settings

Hardware Flow Control

When enabled configures additional 2 GPIO pads for use as RTS/CTS signals for UART

DMA Enable

Enabled: UART OS driver will use DMA when possible. Disabled: OS driver will enforce PIO mode

Power Gating

Timing parameters

D0->D3 idle timeout (screen off)

Default: 200 [DEC] Minimum: 1 [DEC] Maximum: 10000 [DEC]

D0->D3 idle timeout (screen on)

Default: 200 [DEC] Minimum: 1 [DEC] Maximum: 10000 [DEC]

Timing parameters disabled

ISH Controller

Enables/Disables Integrated Sensor Hub (ISH) Device

PDT Unlock Message Enabled

Checked = Sends PDT Unlock Message to ISH. After the message is sent the field is set back to unchecked automatically.

ISH GPIO Assignment Configuration

SPI_0 Enabled

Checked = Pin set to ISH Native function. Checkbox grayed out = disable conflicting SerialIo controller to set. Shared pins: 1. ISH UART0 - LPSS I2C2(PCH-H) 2. ISH UART1 - LPSS UART1 3. ISH I2C2 - LPSS I2C5(PCH-LP) / I2C3(PCH-H)

SPI_0 CS_0 Enabled

UART0 Enabled

UART1 Enabled

I2C0 Enabled

I2C1 Enabled

I2C2 Enabled

GP_0 Enabled

GP_1 Enabled

GP_2 Enabled

GP_3 Enabled

GP_4 Enabled

GP_5 Enabled

GP_6 Enabled

GP_7 Enabled

ISH is not available

Thermal Throttling Level

Determine if use Intel suggested setting

Thermal Throttling Enabled

Enable/Disable the thermal throttling states control

TT State 13 Enabled

PMSync state 13 will force at least T2 state

Thermal Throttling Lock Enabled

Lock the entire TL register

T0 Level

If Trip Point Temperature <= T0Level, the system is in T0 state

T1 Level

If T1Level >= Trip Point Temperature > T0Level, the system is in T1 state

T2 Level

If T2Level >= Trip Point Temperature > T1Level, the system is in T2 state

DMI Thermal Setting

Determine if use Intel suggested setting

DMI Thermal Sensor Autonomous Width Enabled

Enable/Disable Thermal Sensor initiated Autonomous Width Negotiation

Thermal Sensor 0 Width

Determine the DMI Link Width when the output from the Thermal Sensor is T0

Thermal Sensor 1 Width

Determine the DMI Link Width when the output from the Thermal Sensor is T1

Thermal Sensor 2 Width

Determine the DMI Link Width when the output from the Thermal Sensor is T2

Thermal Sensor 3 Width

Determine the DMI Link Width when the output from the Thermal Sensor is T3

SATA Thermal Setting

Determine if use Intel suggested setting

Port 0

T1 Multipler

Determine the value of SATA Port T1 Multipler

T2 Multipler

Determine the value of SATA Port T2 Multipler

T3 Multipler

Determine the value of SATA Port T3 Multipler

Alternate Fast Init Tdispatch Enabled

Enable/Disable SATA Port Alternate Fast Init Tdispatch

Tdispatch

Determine the value of SATA Port Tdispatch

Tinactive

Determine the value of SATA Port Tinactive

Tdispatch

Determine the value of SATA Port Tdispatch

Tinactive

Determine the value of SATA Port Tinactive

Port 1

T1 Multipler

Determine the value of SATA Port T1 Multipler

T2 Multipler

Determine the value of SATA Port T2 Multipler

T3 Multipler

Determine the value of SATA Port T3 Multipler

Alternate Fast Init Tdispatch Enabled

Enable/Disable SATA Port Alternate Fast Init Tdispatch

Tdispatch

Determine the value of SATA Port Tdispatch

Tinactive

Determine the value of SATA Port Tinactive

Tdispatch

Determine the value of SATA Port Tdispatch

Tinactive

Determine the value of SATA Port Tinactive

Touch Pad

Indicates what type of I2C Touch Pad is connected to this SerialIo controller

Touch Pad Interrupt Mode

Selects different routing for interrupts from Touch Pad

Device's bus address

Specify parameters of custom I2C device

Device's HID address

Specify parameters of custom I2C device

Device's bus speed

Specify parameters of custom I2C device

Touch Panel

Indicates what type of I2C Touch Panel is connected to this SerialIo controller

Touch Panel Interrupt Mode

Selects different routing for interrupts from Touch Panel

Device's bus address

Specify parameters of custom I2C device

Device's HID address

Specify parameters of custom I2C device

Device's bus speed

Specify parameters of custom I2C device

Finger Print Sensor

Select the HID to enable Finger Print Sensor

Finger Print Interrupt Mode

Selects different routing for interrupts from Finger Print

Timing parameters

D0->D3 idle timeout (screen off)

Default: 200 [DEC] Minimum: 1 [DEC] Maximum: 10000 [DEC]

D0->D3 idle timeout (screen on)

Default: 2000 [DEC] Minimum: 1 [DEC] Maximum: 10000 [DEC]

Timing parameters disabled

Timing parameters

D0->D3 idle timeout (screen off)

Default: 200 [DEC] Minimum: 1 [DEC] Maximum: 10000 [DEC]

D0->D3 idle timeout (screen on)

Default: 2000 [DEC] Minimum: 1 [DEC] Maximum: 10000 [DEC]

Timing parameters disabled

External V1P05 Rail Sx/S0ix Configuration

Enable Rail in S0i1/S0i2 Enabled

Enables External V1P05 Rail in corresponding Sx/S0ix

Enable Rail in S0i3 Enabled

Enables External V1P05 Rail in corresponding Sx/S0ix

Enable Rail in S3 Enabled

Enables External V1P05 Rail in corresponding Sx/S0ix

Enable Rail in S4 Enabled

Enables External V1P05 Rail in corresponding Sx/S0ix

Enable Rail in S5 Enabled

Enables External V1P05 Rail in corresponding Sx/S0ix

Active Switch Supported Enabled

Enables External V1P05 Rail in corresponding Sx/S0ix

Normal Active Voltage Supported Enabled

Enables External V1P05 Rail in corresponding Sx/S0ix

Minimum Active Voltage Enabled

Enables External V1P05 Rail in corresponding Sx/S0ix

Minimum Retention Voltage Enabled

Enables External V1P05 Rail in corresponding Sx/S0ix

External Vnn Rail Sx/S0ix Configuration

Enable Rail in S0i1/S0i2 Enabled

Enables External Vnn Rail in corresponding Sx/S0ix

Enable Rail in S0i3 Enabled

Enables External Vnn Rail in corresponding Sx/S0ix

Enable Rail in S3 Enabled

Enables External Vnn Rail in corresponding Sx/S0ix

Enable Rail in S4 Enabled

Enables External Vnn Rail in corresponding Sx/S0ix

Enable Rail in S5 Enabled

Enables External Vnn Rail in corresponding Sx/S0ix

Active Switch Supported Enabled

Enables External Vnn Rail in corresponding Sx/S0ix

Normal Active Voltage Supported Enabled

Enables External Vnn Rail in corresponding Sx/S0ix

Minimum Active Voltage Enabled

Enables External Vnn Rail in corresponding Sx/S0ix

Minimum Retention Voltage Enabled

Enables External Vnn Rail in corresponding Sx/S0ix

Override External Vnn Rail settings in Sx states

Enable Rail in S3 Enabled

Enables External Vnn Rail in corresponding Sx/S0ix

Enable Rail in S4 Enabled

Enables External Vnn Rail in corresponding Sx/S0ix

Enable Rail in S5 Enabled

Enables External Vnn Rail in corresponding Sx/S0ix

External Rails Voltage and Current settings

External V1P05 Icc Max Value

Icc Max Value for external V1p05 rail. Expressed in mA. Accepted value are between 0 and 500 mA

External V1P05 Voltage Value

Voltage Value for external V1p05 rail. Specified in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...)

External Vnn Icc Max Value

Icc Max Value for external Vnn rail. Expressed in mA. Accepted value are between 0 and 500 mA

External Vnn Voltage Value

Voltage Value for external Vnn rail. Specified in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...)

External Vnn Sx Icc Max Value

Icc Max Value for external Vnn rail in Sx states. Expressed in mA. Accepted value are between 0 and 500 mA

External Vnn Sx Voltage Value

Voltage Value for external Vnn rail in Sx states. Specified in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...)

VCCIN_AUX voltage rail timing configuration

Retention to Low Current Mode

Transition time in microseconds from Off (0V) to High Current Mode Voltage. This field has 1us resolution.

Retention to High Current Mode

Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage. This field has 1us resolution.

Low to High Current Mode

Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage. This field has 1us resolution.

Off to High Current Mode

Transition time in microseconds from Off (0V) to High Current Mode Voltage. This field has 1us resolution. 0 = Transition to 0V is disabled

FIVR Dynamic PM

Enable/Disable FIVR Dynamic Power Management

ME Firmware Version N/A

ME Firmware Mode Normal Mode

ME Firmware Mode ME ALT Disabled

ME Firmware Mode ME Temporarily Disabled

ME Firmware Mode Secovr Jmpr/Heci MSG

ME Firmware Mode ME Failed

ME Firmware Mode N/A

ME Firmware SKU N/A

ME Firmware Status 1 N/A

ME Firmware Status 2 N/A

ME State

When Disabled ME will be put into ME Temporarily Disabled Mode.

ME Unconfig on RTC Clear

When Disabled ME will not be unconfigured on RTC Clear

Comms Hub Support

Enables/Disables support for Comms Hub.

JHI Support

Enable/Disable Intel(R) DAL Host Interface Service (JHI)

Core Bios Done Message

Enable/Disable Core Bios Done message sent to ME

Firmware Update Configuration

PTT Configuration

FIPS Configuration

Unique Platform Id Configuration

ME Debug Configuration

Anti-Rollback SVN Configuration

Extend CSME Measurement to TPM-PCR

Enable/Disable Extend CSME Measurement to TPM-PCR[0] and AMT Config to TPM-PCR[1]

None

PTT Capability / State N/A

TPM 1.2 Deactivate

Enabling this option will invoke the TPM 1.2 De-activate flow

Me FW Image Re-Flash

Enable/Disable Me FW Image Re-Flash function.

FW Update

Enable/Disable ME FW Update function.

OEM Platform Id N/A

CSME Platform Id N/A

Upid State

Enable/Disable Upid Feature

Upid OS Control State

Allows OS to enable/disable the Upid feature state

HECI Timeouts Enabled

Enable/Disable HECI Send/Receive Timeouts.

Force ME DID Init Status

Forces the DID Initialization Status value.

CPU Replaced Polling Disable

Setting this option disables CPU replacement polling loop

HECI Message check Disable

Setting this option disables message check for Bios Boot Path when sending

MBP HOB Skip

Setting this option will skip MBP HOB

HECI2 Interface Communication Enabled

Adds and Removes HECI2 Device from PCI space.

KT Device Enabled

Enable/Disable KT Device

End Of Post Message

Enable/Disable End of Post message sent to ME

D0I3 Setting for HECI Disable

Setting this option disables setting D0I3 bit for all HECI devices

MCTP Broadcast Cycle

Enable/Disable Management Component Transport Protocol Broadcast Cycle and Set PMT as Bus Owner

FIPS Mode Select

FIPS Mode configuration

FIPS Mode auto sync

When enabled, it always synchronizes FIPS mode automatically. (Spending 250ms at least)

Current FIPS mode Current mode unavailable

Crypto driver FIPS version Version unavailable

Minimal Allowed Anti-Rollback SVN N/A

Executing Anti-Rollback SVN N/A

Automatic HW-Enforced Anti-Rollback SVN

When enabled, hardware-enforced Anti-Rollback mechanism is automatically activated: once ME FW was successfully run on a platform, FW with lower ARB-SVN will be blocked from execution

Set HW-Enforced Anti-Rollback for Current SVN

Enable hardware-enforced Anti-Rollback mechanism for current ARB-SVN value. FW with lower ARB-SVN will be blocked from execution. The value will be restored to disable after the command is sent.

Thermal Configuration

Enable All Thermal Functions

Enable All Thermal Functions" is Enabled it Enables 'Memory Thermal Management','Active Trip Points', 'Critical Trip Points'.Set to disabled for Manual Configuration

CPU Thermal Configuration

Platform Thermal Configuration

Intel(R) Dynamic Tuning Technology Configuration

Hardware Health Monitor

Cpu Thermal Configuration

DTS SMM

Disabled: ACPI thermal management uses EC reported temperature values. Enabled: ACPI thermal management uses DTS SMM mechanism to obtain CPU temperature values. Out of Spec: ACPI Thermal Management uses EC reported temperature values and DTS SMM is used to handle Out of Spec condition.

Tcc Activation Offset

Offset from factory set Tcc activation temprature at which the Thermal Control Circuit must be activated. Tcc will be activated at: Tcc Activation Temp - Tcc Activation Offset. Tcc Activation Offset range is 0 to 63.

Tcc Offset Time Window

Tcc Offset Time Window for Running Average Temperature Limit(RATL) feature. The Tcc offset time window can range from 5ms to 448s.

Tcc Offset Clamp Enable

Tcc Offset Clamp bit Enable for Running Average Temperature Limit(RATL) feature to allow CPU to throttle below P1.

Tcc Offset Lock Enable

Lock Enable for Running Average Temperature Limit(RATL) feature to lock Temperature Target MSR.

Bi-directional PROCHOT#

When a processor thermal sensor trips (either core), the PROCHOT# will be driven. If bi-direction is enabled, external agents can drive PROCHOT# to throttle the processor.

Disable PROCHOT# Output

Enable/Disable PROCHOT# Output

Disable VR Thermal Alert

Enable/Disable VR Thermal Alert

PROCHOT Response

Enable/Disable PROCHOT Response

PROCHOT Lock

Enable/Disable PROCHOT Lock

ACPI T-States Enabled

Enable/Disable ACPI T-States.

Platform Thermal Configuration

Critical Trip Point

This value controls the temperature of the ACPI Critical Trip Point - the point in which the OS will shut the system off. NOTE: 119C is the Plan Of Record (POR) for all Intel mobile processors.

Active Trip Point 0

This value controls the temperature of the ACPI Active Trip Point 0 - the point in which the OS will turn the processor fan on Active Trip Point 0 Fan Speed.

Active Trip Point 0 Fan Speed

Active Trip Point 0 Fan Speed in percentage. Value must be between 0 (Fan off) - 100 (Max fan speed). This is the speed at which fan will run when Active Trip Point 0 is crossed.

Active Trip Point 1

This value controls the temperature of the ACPI Active Trip Point 1 - the point in which the OS will turn the processor fan on Active Trip Point 1 Fan Speed.

Active Trip Point 1 Fan Speed

Active Trip Point 1 Fan Speed in percentage. Value must be between 0 (Fan off) - 100 (Max fan speed). This value must be less than Active Trip Point 0 Fan speed. This is the speed at which fan will run when Active Trip 1 is crossed.

Passive Trip Point

This value controls the temperature of the ACPI Passive Trip Point - the point in which the OS will begin throttling the processor.

Passive TC1 Value

This value sets the TC1 value for the ACPI Passive Cooling Formula. Range 1 - 16

Passive TC2 Value

This value sets the TC2 value for the ACPI Passive Cooling Formula. Range 1 - 16

Passive TSP Value

This item sets the TSP value for the ACPI Passive Cooling Formula. It represents in tenths of a second how often the OS will read the temperature when passive cooling is enabled. Range 2 - 32

Active Trip Points

Disable Active Trip Points

Passive Trip Points

Disable Passive Trip Points

Critical Trip Points

Disable Critical Trip Points

PCH Temp Read Enabled

PCH Temperature Read Enable

CPU Energy Read Enabled

CPU Energy Read Enable

CPU Temp Read Enabled

CPU Temperature Read Enable

Alert Enable Lock

Lock all Alert Enable settings

PCH Alert

PCH Alert pin enable

DIMM Alert

DIMM Alert pin enable

CPU Temp

Fail Safe temp that EC will use if OS is hung

CPU Fan Speed

Fan speed that EC will use if OS is hung

Intel(R) Dynamic Tuning Technology Configuration

Intel(R) Dynamic Tuning Technology

Enable/Disable Intel Dynamic Platform Thermal Framework

INT3400 Device

Enable/Disable the INT3400 Device.

Processor Thermal Device

Enable/Disable Processor Thermal Device.

PPCC Step Size

Step size for Turbo power limit (RAPL) control

Intel(R) Dynamic Tuning Technology Configuration

An Integer containing the Intel(R) Dynamic Tuning Technology Configuration bitmap: BIT0[Generic UI Access Control](0=enable,1=disable) BIT1[Restricted UI Access Control](0=enable,1=disable) BIT2[shell Access Control](0=enable,1=disable) BIT3[Environment Monitoring Report Control](0=report,1=silent) BIT4[Thermal Mitigation Report Control](0=silent,1=report) BIT5[Thermal Policy Report Control](0=silent,1=report)

FAN1 Device

Enable the Fan1 device.

FAN2 Device

Enable the Fan2 device.

FAN3 Device

Enable the Fan3 device.

Charger participant

Enable/Disable Charger device

Power participant

Enable/Disable the Power participant.

Battery Participant

Enable/Disable the Battery Participant.

Intel(R) Dynamic Tuning Technology Battery Sampling Period

This battery sampling period for the Battery Participant Object.

PCH FIVR Participant

Enable/Disable PCH FIVR Participant

Sensor Device 1

Enable/Disable Memory Thermal Device

Sensor Device 2

Enable/Disable VR Hotspot Q50 sensor

Sensor Device 3

Enable/Disable Skin Hotspot U50 sensor

Sensor Device 4

Enable/Disable PMIC-MCP Hotspot Q16 sensor

Sensor Device 5

Enable/Disable C-Skin Chassis U50 IR sensor

Discret Graphics Sensor Device

Enable/Disable DGPU Thermal Sensor

OEM variable and Object

Design Variable 0

OEM Design Variable: an integer between 0-255. This allows OEM's to customize Intel(R) Dynamic Tuning Technology behavior based on platform changes.

Design Variable 1

OEM Design Variable: an integer between 0-255. This allows OEM's to customize Intel(R) Dynamic Tuning Technology behavior based on platform changes.

Design Variable 2

OEM Design Variable: an integer between 0-255. This allows OEM's to customize Intel(R) Dynamic Tuning Technology behavior based on platform changes.

Design Variable 3

OEM Design Variable: an integer between 0-255. This allows OEM's to customize Intel(R) Dynamic Tuning Technology behavior based on platform changes.

Design Variable 4

OEM Design Variable: an integer between 0-255. This allows OEM's to customize Intel(R) Dynamic Tuning Technology behavior based on platform changes.

Design Variable 5

OEM Design Variable: an integer between 0-255. This allows OEM's to customize Intel(R) Dynamic Tuning Technology behavior based on platform changes.

PPCC Object

Enable/Disable PPCC object for validation.

ARTG Object

Enable/Disable ARTG object for validation.

PMAX Object

Enable/Disable PMAX object for validation.

Processor Thermal Device

_TMP 1 Object

Enable/Disable _TMP 1 object for validation.

_TMP 2 Object

Enable/Disable _TMP 2 object for validation.

_TMP 3 Object

Enable/Disable _TMP 3 object for validation.

_TMP 4 Object

Enable/Disable _TMP 4 object for validation.

_TMP 5 Object

Enable/Disable _TMP 5 object for validation.

_TMP 6 Object

Enable/Disable _TMP 6 object for validation.

_TMP 7 Object

Enable/Disable _TMP 7 object for validation.

_TMP 8 Object

Enable/Disable _TMP 8 object for validation.

Optional Objects

Enable/Disable PIPR/PAPR for processor participant.

Platform Settings

Charging Method

Select charging method as Normal Charging or Fast Charging.

PS2 Keyboard and Mouse

Enables/Disables PS2 Keyboard and Mouse

Power Loss Notification Feature

Enable/Disable Power Loss Notification Feature

Device password support Enabled

Support device password feature

Pmic Vcc IO Level

Select the Pmic Vcc IO Voltage Level

Pmic Vddq Level

Select the Pmic Vddq Voltage Level

HEBC value

HEBC value 32bit

Pmic SlpS0 VM Support

Support to auto check Primium PMIC and disable SlpS0 voltage.

Power Sharing Manager

Configure the PSM ACPI objects.

Domain Type SPLC 1

09h: Module(M.2); 07h: WiFi/WLAN; 0Fh: WWAN; 10h WiGig; 14h: RFEM

Default Power Limit 1 SPLC

Power Limit in milli watts

Default Time Window 1 SPLC

Time Window in milli seconds

Domain Type DPLC 1

09h: Module(M.2); 07h: WiFi/WLAN; 0Fh: WWAN; 10h WiGig; 14h: RFEM

Domain Preference DPLC 1

09h: Module(M.2); 07h: WiFi/WLAN; 0Fh: WWAN; 10h WiGig; 14h: RFEM

Power Limit Index 1 DPLC

Index of the specific power limit range information

Default Power Limit 1 DPLC

Power Limit in milli watts

Default Time Window 1 DPLC

Time Window in milli seconds

Minimum Power Limit 1 DPLC

Power Limit in milli watts

Maximum Power Limit 1 DPLC

Power Limit in milli watts

Maximum Time Window 1 DPLC

Time Window in milli seconds

Enable FFU Support

Enable/Disable FFU Support.

HID Event Filter Driver

Enables/Disables HID Event Filter Driver interface to OS.

Delay to wait for WWAN device to be ready before SAR reset.

Value between 0-255 seconds. Default is 8. Will result in Responsiveness impact.

System Time and Alarm Source

Select source of system time and alarm functions. ACPI Time and Alarm (default, legacy RTC disabled) or Legacy RTC support only

Enable xdpclock

Enable xdpclock routing on slot1 CMU_ONE_DWORD0 bits muxsel_itpxdp

Enable PowerMeter

Disable PCIE Tunneling Over USB4

Setting this option disables retry PCIE Tunneling Over USB4

Intel Trusted Device Setup Boot

Enables/Disables a Intel Trusted Device Setup Boot on the next boot

System Firmware Update Config

TCSS Platform Setting

ACPI D3Cold settings

ACPI D3Cold Support

Enable/Disable ACPI D3Cold support to be executed on D3 entry and exit

VR Ramp up delay

Delay between subsequent VR ramp ups if they are all Turn ON at the same time

PCIE Slot 5 Device Power-on delay in ms

Delay between applying core power and Deasserting PERST#

Audio Delay

Delay after applying power to HD Audio(Realtek) codec device.

SensorHub

Delay after applying power to SensorHub device.

TouchPad

Delay after applying power to TouchPad device.

TouchPanel

Delay in PR _ON after applying power to TouchPanel device.

P-state Capping

Set _PPC and send ACPI notification

USB Port 1

USB RTD3 support. Super Speed : USB3.0 devices will be exposed as RTD3 capable. High Speed: USB2.0 devices will be exposed as RTD3 capable. Disabled : USB RTD3 support disabled. For SawtoothPeak USB Port1(Below) is Superspeed and Port2(Top) is HighSpeed. Check respective board configuration to know about USB port position.

USB Port 2

ZPODD

Zero Power ODD option is applicable only for the board with ZPODD support.

WWAN

Enable/Disable RTD3 support for WWAN

Sata Port 0

Setup option to control the SATA port RTD3 functionality

Sata Port 1

Setup option to control the SATA port RTD3 functionality

Sata Port 2

Setup option to control the SATA port RTD3 functionality

Sata Port 3

Setup option to control the SATA port RTD3 functionality

Sata Port 4

Setup option to control the SATA port RTD3 functionality

Sata Port 5

Setup option to control the SATA port RTD3 functionality

PCIe Remapped CR1

PCIe RTD3 setup conflicts with SATA RTD3. Platform specific.

PCIe Remapped CR2

PCIe RTD3 setup conflicts with SATA RTD3. Platform specific.

PCIe Remapped CR3

PCIe RTD3 setup conflicts with SATA RTD3. Platform specific.

DTBT RTD3 Enable

Enables or Disables DTBT RTD3 support

TBT Power-off delay in ms

Specify delay in ms necessary after removing TBT power

DTBT RTD3 CLKREQ Enable

Enables or Disables DTBT RTD3 CLKREQ mask

DTBT RTD3 CLKREQ Delay value

Specify delay in ms necessary after CLKREQ mask state is changed.

System Firmware Update Config

Restore Setup Default

Restore Setup default settings after System Firmware Update

Skip Power Check

Skip AC/DC Check before System Firmware Update

TCSS Platform Setting

Control Iommu Pre-boot Behavior

Enable IOMMU in Pre-boot environment (If DMAR table is installed in DXE and If VTD_INFO_PPI is installed in PEI.)

USBC connector manager selection

Select UCSI or UCMC device in ACPI support based on configuration

UCMC PD Interrupt Pin

R-09 Rework

PD PS_ON mode selection

Select TCSS PD Policy on Low Power Entry

Thunderbolt(TM) Configuration

PD Information

PD0 Application name N/A

PD0 External Circuit Specific Version N/A

PD0 Version N/A

PD1 Application name N/A

PD1 External Circuit Specific Version N/A

PD1 Version N/A

USBC and USBA Wake Capability

Hardware Health Monitor

Thermal Sensor 1 Temp

Help on Thermal Sensor 1 Temp

Thermal Sensor 2 Temp

Help on Thermal Sensor 2 Temp

Thermal Sensor 3 Temp

Help on Thermal Sensor 3 Temp

Thermal Sensor 4 Temp

Help on Thermal Sensor 4 Temp

Thermal Sensor 5 Temp

Help on Thermal Sensor 5 Temp

CPU Fan Speed

Help on CPU Fan

PCH DTS Temp from PCH

Help on PCH DTS Temp

Discrete Thunderbolt(TM) Support

Enable or Disable Discrete Thunderbolt(TM) Support.

Wake From Thunderbolt(TM) Devices Enabled

Enable or disable system wake from Thunderbolt(TM) devices.

Current Security Level

Display Current Security Level.

Native OS security for TBT

Enable Native OS security solution for Thunderbolt hosts

Discrete Thunderbolt(TM) Configuration

Thunderbolt Usb Support

Enabled allows boot from Usb devices which is present behind Thunderbolt

Thunderbolt Boot Support

Enabled allows boot from Bootable devices which is present behind Thunderbolt

Titan Ridge Workaround for OSUP

Enable or Disable Titan Ridge Workaround for OSUP

Tbt Dynamic AC/DC L1

Enable or Disable Tbt Dynamic AC/DC L1 Support

ACPI Removal Object Suppport

Enable or Disable ACPI method _RMV support for Thunderbolt(TM) devices

GPIO3 Force Pwr Enabled

Set GPIO3 to 1/0

Wait time in ms after applying Force Pwr

After Force Pwr is asserted the wait time (in milli seconds) before access the TBT controller

GPIO filter

GPIO filter is needed to avoid electrical noise on PCH GPIOs during hotplug of 12V USB devices

DTBT Controller 0 Configuration

DTBT Controller 1 Configuration

Thunderbolt(TM) OS select

Windows 10 Thunderbolt support

DTBT Controller 0

AUTO - Default, Enable - RVP3 PCIe Root Port1, CNL RVP5 - PCIe Root Port5, CNL SDS - PCIe Root Port5

DTbt Root Port Type

Select the TBT Root Port Type. PCH or PEG

TBT Host Router

Enable the host router based on ports available.

Extra Bus Reserved

Extra Bus Reserved 56-One port Host,106-Two port Host.

Reserved Memory

Reserved Memory for this Root Bridge (1-4096) MB

Memory Alignment

Memory Alignment (0-31 bits)

Reserved PMemory

Reserved Prefetchable Memory for this Root Bridge (1-4096) MB

PMemory Alignment

PMemory Alignment (0-31 bits)

DTBT Controller 1

None

DTbt Root Port Type

Select the TBT Root Port Type. PCH or PEG

TBT Host Router

Enable the host router based on ports available.

Extra Bus Reserved

Extra Bus Reserved 56-One port Host,106-Two port Host.

Reserved Memory

Reserved Memory for this Root Bridge (1-4096) MB

Memory Alignment

Memory Alignment (0-31 bits)

Reserved PMemory

Reserved Prefetchable Memory for this Root Bridge (1-4096) MB

PMemory Alignment

PMemory Alignment (0-31 bits)

ICC Profile

Select clock profile that corresponds to the platform configuration. Profiles are defined by the OEM and platform capabilites. Tpically, profile 0 has failsafe settings. Other profiles correspond to WiMax, 3G, or Overclocking settings.

PCH CSME - BCLK Clock Settings

Default Clock Settings 100.00MHz 0.50% Downspread

Frequency Range Limits uninitialized MHz

Maximum Spread % uninitialized %

Spread Mode Adjustments Uninitialized

Clock Frequency

Frequency in 10kHz increments. Specifies new BCLK frequency to be applied. Frequency is rounded to nearest valid value. Allowed range is limited by the Max/Min supported frequencies. Changes are not applied until settings are saved and platform resets. Example: For 125.70MHz, enter 12570.

Bclk Change Permanent

Changes how the BCLK frequency changes are applied permanent with warm reset. 0 - Disabled. 1 - Enabled.

Bclk Change w/o Reset

Changes how the BCLK frequency changes are applied. 0 - Realtime. 1 - Permanent, without warm reset. NOTE: Realtime changes will be applied when 'F4' hotkey is pressed. Uses MEI SET_CLOCK_SETTINGS command 0x1B.

Spread %

Specifies the amount of spread spectrum clocking to be applied to the base clock frequency in 0.01% increments. Allowed range is limited by Maximum Spread % and supported Spread mode Adjustements. If Changes Allowed, a value between 0 and Max Spread % can be specified. Value is adjusted to settings supported by HW. If only Halt Allowed, only 0% and default spread % can be specified. Changes are not applied until settings are saved and platform resets.

Rework Information

Board Rework Compliance

To Enable/ Disable Board Rework Complaince Suppport.

Mandatory Board Rework: N/A

Reworks present on the board: N/A

Missing Board Reworks: N/A

Clevo Support

Clevo SHOW SETUP ITEM Support

Show TerransForce MemInfo item

OEM Serial Type 1

Enable/Disable to display OEM Serial Number (TYPE 1)

OEM Serial Type 2

Enable/Disable to display OEM Serial Number (TYPE 2)

Show Advanced item

Show Advanced item or Not.

Show CPU XDB item

Show CPU XDB item or Not.

Show CPU VT item

Show CPU VT item or Not.

Show CPU VT-D item

Show CPU VT-D item or Not.

Show FAST BOOT item

Show FAST BOOT item or Not.

Show CPU TXT item

Show CPU TXT item or Not.

Show CPU HP item

Show CPU HP item or Not.

Show HDD PASSWORD item

Show HDD PASSWORD item or Not.

Show CPU TURBO item

Show CPU TURBO item or Not.

Show CPU SGX item

Show CPU SGX item or Not.

Show SATA port 0 item

Show SATA port item or Not.

Show SATA port 1 item

Show SATA port item or Not.

Show SATA port 2 item

Show SATA port item or Not.

Show SATA port 3 item

Show SATA port item or Not.

Show SATA port 4 item

Show SATA port item or Not.

Show SATA port 5 item

Show SATA port item or Not.

Show SATA port 6 item

Show SATA port item or Not.

Show SATA port 7 item

Show SATA port item or Not.

Show LAUNCH CSM item

Show LAUNCH CSM item or Not.

Show UEFI MODE item

Show UEFI MODE item or Not.

Show BOOT_LOGO item

Show BOOT_LOGO item or Not.

Show GRAPHICSMODESWITCH item

Show GRAPHICSMODESWITCH item TYPE 1 MSHYBRID/DGPU MODE/ TYPE 2 IGD/MSHYBRID MODE / TYPE 3 ALL TYPE 4 HIDDEN.

Show RAID MODE item

Show RAID MODE item ENABLE / DISABLE RAID MODE SELECT

Show Vmd Page item

Show Vmd Page item ENABLE / DISABLE

Alwasy Show SATA port page item

Alwasy Show SATA port Page item ENABLE / DISABLE

Alwasy Show Off Board SATA Page item

Alwasy Show Off Board SATA Page item ENABLE / DISABLE

Alwasy Show Off Board NVMe Page item

Alwasy Show Off Board NVMe Page item ENABLE / DISABLE

iGD OpRegion BCLM Table Override

BCLM 0

BCLM 1

BCLM 2

BCLM 3

BCLM 4

BCLM 5

BCLM 6

BCLM 7

BCLM 8

BCLM 9

BCLM 10

Show Power On Beep item

Show Power On Beep item ENABLE / DISABLE

Show Uefi Setting item

Show Uefi Setting item ENABLE / DISABLE

Show USB_BOOT item

Show USB_BOOT item or Not.

Show USB TYPEC PORT 1 ENABLE/DISABLE STRING item

Show USB TYPEC PORT 1 ENABLE/DISABLE STRING item or Not.

Show USB TYPEC PORT 2 ENABLE/DISABLE STRING item

Show USB TYPEC PORT 2 ENABLE/DISABLE STRING item or Not.

Show USB 3.0 PORT 1 ENABLE/DISABLE STRING item

Show USB 3.0 PORT 1 ENABLE/DISABLE STRING item or Not.

Show USB 3.0 PORT 2 ENABLE/DISABLE STRING item

Show USB 3.0 PORT 2 ENABLE/DISABLE STRING item or Not.

Show CUSTOMER PC ART ITEM ENABLE/DISABLE STRING item

Show CUSTOMER PC ART ITEM ENABLE/DISABLE STRING item or Not.

Show USB WEBCAM ENABLE/DISABLE STRING item

Show USB WEBCAM ENABLE/DISABLE STRING item or Not.

Show USB Bluetooth Device ENABLE/DISABLE STRING item

Show USB Bluetooth Device ENABLE/DISABLE STRING item or Not.

Show USB 4G/3G CARD ENABLE/DISABLE STRING item

Show USB 4G/3G CARD ENABLE/DISABLE STRING item or Not.

Show INTEL HWP ENABLE/DISABLE STRING item

Show INTEL HWP ENABLE/DISABLE STRING item or Not.

Show GPU Performance Scaling ENABLE/DISABLE STRING item

Show GPU Performance Scaling ENABLE/DISABLE STRING item or Not.

Show WLAN ENABLE/DISABLE STRING item

Show WLAN ENABLE/DISABLE STRING item or Not.

Show USB FINGER PRINTER DEVICE ENABLE/DISABLE STRING item

Show USB FINGER PRINTER DEVICE ENABLE/DISABLE STRING item or Not.

Show AUDIO DEVICE CONTROL

AUDIO DEVICE Enable/Disable

Show Wake On Lan

Wake On Lan Enable/Disable

Show Cardreader DEVICE CONTROL

Cardreader DEVICE Enable/Disable

Show Glan DEVICE CONTROL

Glan DEVICE Enable/Disable

Show Microphone CONTROL

Microphone Enable/Disable(only supoort DMIC)

Show ODD (CR-ROM)DEVICE CONTROL

ODD (CR-ROM)DEVICE Enable/Disable

Show DEVICE CONTROL

ODD/CARDER/LAN/WOL/USB Enable/Disable

Show ME STATE ENABLE/DISABLE STRING item

Show ME STATE ENABLE/DISABLE STRING item or Not.

Show HYPERPFERMANCE ENABLE/DISABLE STRING item

Show HYPERPFERMANCE ENABLE/DISABLE STRING item or Not.

Show NV VGA INFORMATION item

Show NV VGA INFORMATION item or Not.

Show BackLight Keyboard Function ENABLE/DISABLE item

Show BackLight Keyboard Function item or Not.

Show CUSTOMER INFORMATION STRING item

Show CUSTOMER INFOR SHOW 0:NORMAL 1:HAIER.

Show CD-ROM BOOT item

Show CD-ROM BOOT item or Not.

Show AC FAN Disabled fan idle mode and fan off item

Show AC FAN Disabled fan idle mode and fan off item or Not.

Show Battery Saver item

SMBIOS 248 ACDisableFlag

SMBIOS 248 CountryCodeFlag

SMBIOS 248 CountryCodeVaule

Custom Boot Manager ScanCode

Custom Boot Manager ScanCode with Ctrl or Alt or Shift

Custom Front Page ScanCode

Custom Front Page ScanCode with Ctrl or Alt or Shift

Custom Lan Pxe ScanCode

Custom Lan Pxe ScanCode with Ctrl or Alt or Shift

Custom OS Recovery ScanCode

Custom OS Recovery ScanCode with Ctrl or Alt or Shift

FULL MENU HotKey Support

Custom FULL MENU ScanCode

Custom FULL MENU ScanCode with Ctrl or Alt or Shift

BoardID:

KEYBOARDTYPE

BACKLIGHT KEYBOARD TYPE 0: NO LED LIGHT KEYBOARD 1:RGB KEYBOARD 2:WITHE KEYBOARD 6:ALL AREA RGB KEYBOARD

TPM DEVICE BOARD ID:

Clevo SHOW SETUP ITEM Support

FANLESS DEVICE BOARD ID:

Clevo SHOW SETUP ITEM Support

EDP DEVICE BOARD ID:

Clevo SHOW SETUP ITEM Support

EMMC DEVICE BOARD ID:

Clevo SHOW SETUP ITEM Support

CNVI DEVICE BOARD ID:

Clevo SHOW SETUP ITEM Support

CLEVO HIBERNATEFLAG

Clevo SHOW SETUP ITEM Support

OEM USBDEVICE

Combo slot

Please select the correct device in the slot. After changing the option, shut the unit down, remove the AC/DC adapter and then plug it in again.

UEFI Setting

If UEFI Boot set Enable, it's in UEFI Mode with secure boot

Keep Touch Pad status

Enable or Disable Keep Touch Pad status.

Webcam Power Notify EC Device State Enable:1 / Disable :0

Bluetooth Power Notify EC Device State Enable:1 / Disable :0

3G Power Notify EC Device State Enable:1 / Disable :0

ACPI OEMID/OEMTBLID Override

Enable show MSDN TABLE

CUSTOMER REQUEST NO INSERT OA 30 KEY AND ALWAYS SHOW MSDN TABLE

Oem ACPI OEMID Byte0

Oem ACPI OEMID Byte1

Oem ACPI OEMID Byte2

Oem ACPI OEMID Byte3

Oem ACPI OEMID Byte4

Oem ACPI OEMID Byte5

Oem ACPI OEMTBLID Byte0

Oem ACPI OEMTBLID Byte1

Oem ACPI OEMTBLID Byte2

Oem ACPI OEMTBLID Byte3

Oem ACPI OEMTBLID Byte4

Oem ACPI OEMTBLID Byte5

Oem ACPI OEMTBLID Byte6

Oem ACPI OEMTBLID Byte7

Modify Customer IGD SSID SVID VALUE

DUMMY_DATA

IccMax

Built-in Shell Supoport

Enable or Disable Built-in Shell Supoport.

USB TYPEPRIORITY

HD TYPEPRIORITY

PXE TYPEPRIORITY

CD TYPEPRIORITY

OTHER TYPEPRIORITY

USB PRIORITY1

USB PRIORITY2

USB PRIORITY3

USB PRIORITY4

USB PRIORITY5

USB PRIORITY6

USB PRIORITY7

USB PRIORITY8

FanLess Mode:

With Fan : Enable / Without Fan : Disable / AUTO:CPU ID DETECT SELECT FAN EXIST OR NOT

TjMax 105 Tcc

CCD ID NUMBER

DETECT CCD PID VID LOAD VERBTABLE

BacklightKeyboardtimer

WINDBG SUPPORT NOTIFY EC NOT TO SHUTDOWN

ACPI TABLE SLIC SUPPORT (SLP20)

IF CUSTOMER SUYPPORT SLP20 PLEASE ENABLE THIS ITEM ELSE DIASLE

CLEVO NV OVER POWER GPIO SETTING

SET NV VGA CARD OVER POWER CONFIG BY GPIO SETTING

VBT Select

Select VBT for GOP Driver

OEM to select the DPS Panel Type

Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.

OEM to select the DPST Panel Function

This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled set AUTO by VBT defulat

OEM to select the PSR Panel Function

his feature determines whether Panel Self Refresh (PSR) feature is enabled or disabled. set AUTO by VBT defulat

OEM to select the DRRS Panel Function

This feature determines whether Intel Display Refresh Rate Switching (DRRS) is enabled or disabled. set AUTO by VBT defulat

OEM to select the DMRRS Panel Function

Ihis feature determines whether Dynamic media refresh rate switching is enabled or disabled. set AUTO by VBT defulat

OEM to select the DPST LEVEL Select

selection of DPST Aggressiveness level 1 ~ 6 (1 - max quality with no DPST / 6 - max battery) set AUTO by VBT defulat

OEM FORCE SETUP VALUE SETTING Panel Power Saving Function

This feature determines VBT panel setting override by setup defulat setting (only for debug use)

OEM Refresh Rate bitmap VBT Setting Override

Refresh Rate bitmap selection (0 = Do not remove, 1 = Remove) Rate(Hz) Bit15:Rsvd/Bit14:48/Bit13:25/Bit12:24/Bit11:50/Bit10:40/Bit9:30/Bit8:120/Bit7:100/Bit6:85/Bit5:75/Bit4:72/Bit3:70/Bit2:60/Bit1:56/Bit0:43

OEM Removal Flags bitmap VBT Setting Override

Removal Flags bitmap selection (0 = Do not remove, 1 = Remove) Component Bit7:Rsvd/Bit6:TV Scan Mode/Bit5:LFP/Bit4:EFP/Bit3:Rsvd/Bit2:Rsvd/Bit1:Driver/Bit0:VBIOS

IccMax SA PROTECT POINT

IccMax SET IN SETUP PASSE TO ACPI TABLE FOR RUNTIME PROTECT 0:SKIP PROTECT / < 0 WILL NUMBER OF IA

IccMax IA PROTECT POINT

IccMax SET IN SETUP PASSE TO ACPI TABLE FOR RUNTIME PROTECT 0:SKIP PROTECT / < 0 WILL NUMBER OF IA

IccMax RING PROTECT POINT

IccMax SET IN SETUP PASSE TO ACPI TABLE FOR RUNTIME PROTECT 0:SKIP PROTECT / < 0 WILL NUMBER OF IA

IccMax GT PROTECT POINT

IccMax SET IN SETUP PASSE TO ACPI TABLE FOR RUNTIME PROTECT 0:SKIP PROTECT / < 0 WILL NUMBER OF IA

IccMax FIVR PROTECT POINT

IccMax SET IN SETUP PASSE TO ACPI TABLE FOR RUNTIME PROTECT 0:SKIP PROTECT / < 0 WILL NUMBER OF IA

CLEVO Windows firmware update behavior

CLEVO Windows firmware update behavior. Behavior is AC adpater and battery low power, Behavior is AC adpater or battery low power.

CUSTOM RAM 1

CUSTOMER RAM INFORMATION SHOW.

CUSTOM RAM 2

CUSTOMER RAM INFORMATION SHOW.

CUSTOM RAM 3

CUSTOMER RAM INFORMATION SHOW.

CUSTOM RAM 4

CUSTOMER RAM INFORMATION SHOW.

NV GPU POST Brightness

Lan Pxe HotKey Support

OS Recovery HotKey Support

OS Recovery by Customer rule

OS Recovery Boot File Path

CLEVO Secure Boot Setting Support

CLEVO Support Secure Boot en/dis and default factory key load.

CLEVO Secure Boot Enance Enable/Disable

CLEVO Secure Boot Enance defulat value.

CLEVO Restore Secure Boot to Factory Settings

CLEVO Restore all of the Secure Boot Settings to default factory settings and enable Secure Boot.

FN_3_HOKEY FUNCTION

FN_3_HOKEY ENABLE/DISABLE FUNCTION.

BATTERY LOW BRIGHTNESS NOTIFY DISABLE FUNCTION

BATTERY LOW BRIGHTNESS NOTIFY ENABLE/DISABLE FUNCTION.(Q EVENT 19/1E

CC3.0 SUPPORT UWP APP

UWP apps required for this model BIT0:OSD BIT1:Flexikey BIT2:FlexiAccess BIT3:Per-key BIT4:RGB Keyboard BIT5:GPU OC BIT6:CPU OC BIT7:Fan Speed

REPORT OS BATTERY FULL CAP

REPORT OS FULL CAP Multiplication value Percentage 0 ~ 100%

REPORT OS BATTERY Percentage down brightness to 0

REPORT OS DOWN brightness when batery value Percentage 0:no function 0>: 1 ~ 100% down panel brightness,battery life use

CC3.0 SUPPORT UWP APP ENABLE /DISABLE

UWP apps required for this model

CUSTOMER CC3.0 POWER MODE AP DEFULAT

Report AP CUSTOMER CC.30 HYPER PERMANCE DEFULAT MODE

CUSTOMER AP DEFULAT MODE DEFULAT

Report AP CUSTOMER SETTING DEFULAT MODE

NumPad3Col

NumPad3Col selection

USB PORT 1 USB 3.0 TX Output -3.5dB De-Emphasis Adjustment

TX Output -3.5dB De-Emphasis Adjustment Setting 0~3F

USB PORT 1 USB 3.0 TX Output Downscale Amplitude Adjustment

TX Output Downscale Amplitude Adjustment Setting 0~3F (SWING voltage)

USB PORT 2 USB 3.0 TX Output -3.5dB De-Emphasis Adjustment

TX Output -3.5dB De-Emphasis Adjustment Setting 0~3F

USB PORT 3 USB 3.0 TX Output Downscale Amplitude Adjustment

TX Output Downscale Amplitude Adjustment Setting 0~3F (SWING voltage)

USB PORT 3 USB 3.0 TX Output -3.5dB De-Emphasis Adjustment

TX Output -3.5dB De-Emphasis Adjustment Setting 0~3F

USB PORT 2 USB 3.0 TX Output Downscale Amplitude Adjustment

TX Output Downscale Amplitude Adjustment Setting 0~3F (SWING voltage)

USB PORT 4 USB 3.0 TX Output -3.5dB De-Emphasis Adjustment

TX Output -3.5dB De-Emphasis Adjustment Setting 0~3F

USB PORT 4 USB 3.0 TX Output Downscale Amplitude Adjustment

TX Output Downscale Amplitude Adjustment Setting 0~3F (SWING voltage)

NV CARD GPIO POWER CTRL ENABLE /DISABLE

NV CARD GPIO POWER CTRL SUPPORT GPIO POWER _EN /RST PING

POST LOGO SHOW SUB FUNCTION BY CUSTOMER

CUSTOME LOGO CHANGE MODE SMBIOS/RESUTION/DEFULAT

POST LOGO RESLUTION SELECT DETECT

CUSTOME LOGO CHANGE RESLUTION MODE SELECT BY GRAPHIC MODE

POST LOGO LOCATION SELECT DEFINE

LOGO CHANGE LOCATION SELECT CLEVO DEFINE MAYBE LOST LOGO ENTER OS

Clevo I3 CPU CC3.0 Settings

Clevo I5 CPU CC3.0 Settings

Clevo I7 CPU CC3.0 Settings

Clevo Celeron CPU CC3.0 Settings

N960KP Clevo I3 CPU CC3.0 Settings

N960KP Clevo I5 CPU CC3.0 Settings

N960KP Clevo I7 CPU CC3.0 Settings

N960KP Clevo Celeron CPU CC3.0 Settings

DPTF QUIET Mode Platform PL1 MIN POWER

DPTF PPCC PL1 MIN VALUE REPORT DPTF DRIVER

DPTF QUIET Mode Platform PL1 MAX POWER

DPTF PPCC PL1 MAX VALUE REPORT DPTF DRIVER

DPTF QUIET Mode Platform PL2 MAX POWER

DPTF PPCC PL2 MAX VALUE REPORT DPTF DRIVER

DPTF QUIET Mode Platform PL2 MAX POWER

DPTF PPCC PL2 MAX VALUE REPORT DPTF DRIVER

DPTF POWER_SAVING Mode Platform PL1 MIN POWER

DPTF PPCC PL1 MIN VALUE REPORT DPTF DRIVER

DPTF POWER_SAVING Mode Platform PL1 MAX POWER

DPTF PPCC PL1 MAX VALUE REPORT DPTF DRIVER

DPTF POWER_SAVING Mode Platform PL2 MAX POWER

DPTF PPCC PL2 MAX VALUE REPORT DPTF DRIVER

DPTF POWER_SAVING Mode Platform PL2 MAX POWER

DPTF PPCC PL2 MAX VALUE REPORT DPTF DRIVER

DPTF PERFORMANCE Mode Platform PL1 MIN POWER

DPTF PPCC PL1 MIN VALUE REPORT DPTF DRIVER

DPTF PERFORMANCE Mode Platform PL1 MAX POWER

DPTF PPCC PL1 MAX VALUE REPORT DPTF DRIVER

DPTF PERFORMANCE Mode Platform PL2 MAX POWER

DPTF PPCC PL2 MAX VALUE REPORT DPTF DRIVER

DPTF PERFORMANCE Mode Platform PL2 MAX POWER

DPTF PPCC PL2 MAX VALUE REPORT DPTF DRIVER

DPTF ENTERTAINMENT Mode Platform PL1 MIN POWER

DPTF PPCC PL1 MIN VALUE REPORT DPTF DRIVER

DPTF ENTERTAINMENT Mode Platform PL1 MAX POWER

DPTF PPCC PL1 MAX VALUE REPORT DPTF DRIVER

DPTF ENTERTAINMENT Mode Platform PL2 MAX POWER

DPTF PPCC PL2 MAX VALUE REPORT DPTF DRIVER

DPTF ENTERTAINMENT Mode Platform PL2 MAX POWER

DPTF PPCC PL2 MAX VALUE REPORT DPTF DRIVER

DPTF PL1 POWER STEP SIZE

DPTF PPCC PL1 STEP_SIZE VALUE REPORT DPTF DRIVER

DPTF PL2 POWER STEP SIZE

DPTF PPCC PL2 STEP_SIZE VALUE REPORT DPTF DRIVER

DPTF PSVT CPU BOOST HI TEMP DEGREE

REPORT DTT PSVT CPU BOOST HI TEMP LIMIT (K)

DPTF PSVT CPU BOOST LOW TEMP DEGREE

REPORT DTT PSVT CPU BOOST LOW TEMP LIMIT (K)

DPTF PSVT CPU BOOST HI TEMP PL1 POWER LIMIT

REPORT DTT PSVT CPU BOOST HI TEMP PL1 POWER LIMIT (WATT)

DPTF PSVT CPU BOOST LOW TEMP PL1 POWER LIMIT SETTING

REPORT DTT PSVT CPU BOOST LOW TEMP PL1 POWER LIMIT (WATT)

DPTF SEN2 HYSTERESIS_DEGREE

DPTF SETTING HYSTERESIS_DEGREE OFFSET

TURBO SUPOORT MODE

CUSTOMER CPU TURBO CONFIG BIT0:Quiet BIT1:Power Saving BIT2:Performance BIT3:Entertainment || 1:ENABLE 0:DISABLE

NV GPS TEMP PSV DEGREE

NV GPS REPORT TEMP. DRGREE 70~87(N18) 92(N17)

NV N17 GPS TEMP PSV DEGREE

NV GPS REPORT TEMP. DRGREE 70~87(N18) 92(N17)

Load Storm Tcc Ctrl Support

Enable/Disable Dynamic control TCC offset to decrease fan noise.

Load Storm Tcc Offset

Set Tcc offset for out of Load Storm mode.Range 1~55. Set value with extra +5oC. Ex:offset = 35oC, please set to 40oC

Load Storm Tcc Offset Step

Set Tcc offset recover temp by every time called from EC

QUIET Mode Power Limit 1

QUIET Mode Power Limit 1 Time Window

Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.

QUIET Mode Power Limit 2

QUIET Mode Platform PSYS PL1 Power

QUIET Mode Platform PL1 Time Window

Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default values. Indicates the time window over which Platform TDP value should be maintained.

QUIET Mode Platform PSYS PL2 Power

QUIET Mode IA ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

QUIET Mode GT ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

QUIET Mode Default Tcc

Power Saving Mode Power Limit 1

Power Saving Mode Power Limit 1 Time Window

Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.

Power Saving Mode Power Limit 2

Power Saving Mode Platform PSYS PL1 Power

Power Saving Mode Platform PL1 Time Window

Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default values. Indicates the time window over which Platform TDP value should be maintained.

Power Saving Mode Platform PSYS PL2 Power

Power Saving Mode IA ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Power Saving Mode GT ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Power Saving Mode Default Tcc

Performance Mode Power Limit 1

Performance Mode Power Limit 1 Time Window

Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.

Performance Mode Power Limit 2

Performance Mode Platform PSYS PL1 Power

Performance Mode Platform PL1 Time Window

Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default values. Indicates the time window over which Platform TDP value should be maintained.

Performance Mode Platform PSYS PL2 Power

Performance Mode IA ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Performance Mode GT ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Performance Mode Default Tcc

Entertainment Mode Power Limit 1

Entertainment Mode Power Limit 1 Time Window

Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.

Entertainment Mode Power Limit 2

Entertainment Mode Platform PSYS PL1 Power

Entertainment Mode Platform PL1 Time Window

Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default values. Indicates the time window over which Platform TDP value should be maintained.

Entertainment Mode Platform PSYS PL2 Power

Entertainment Mode IA ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Entertainment Mode GT ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Entertainment Mode Default Tcc

QUIET Mode Power Limit 1

QUIET Mode Power Limit 1 Time Window

Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.

QUIET Mode Power Limit 2

QUIET Mode Platform PSYS PL1 Power

QUIET Mode Platform PL1 Time Window

Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default values. Indicates the time window over which Platform TDP value should be maintained.

QUIET Mode Platform PSYS PL2 Power

QUIET Mode IA ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

QUIET Mode GT ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

QUIET Mode Default Tcc

Power Saving Mode Power Limit 1

Power Saving Mode Power Limit 1 Time Window

Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.

Power Saving Mode Power Limit 2

Power Saving Mode Platform PSYS PL1 Power

Power Saving Mode Platform PL1 Time Window

Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default values. Indicates the time window over which Platform TDP value should be maintained.

Power Saving Mode Platform PSYS PL2 Power

Power Saving Mode IA ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Power Saving Mode GT ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Power Saving Mode Default Tcc

Performance Mode Power Limit 1

Performance Mode Power Limit 1 Time Window

Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.

Performance Mode Power Limit 2

Performance Mode Platform PSYS PL1 Power

Performance Mode Platform PL1 Time Window

Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default values. Indicates the time window over which Platform TDP value should be maintained.

Performance Mode Platform PSYS PL2 Power

Performance Mode IA ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Performance Mode GT ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Performance Mode Default Tcc

Entertainment Mode Power Limit 1

Entertainment Mode Power Limit 1 Time Window

Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.

Entertainment Mode Power Limit 2

Entertainment Mode Platform PSYS PL1 Power

Entertainment Mode Platform PL1 Time Window

Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default values. Indicates the time window over which Platform TDP value should be maintained.

Entertainment Mode Platform PSYS PL2 Power

Entertainment Mode IA ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Entertainment Mode GT ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Entertainment Mode Default Tcc

QUIET Mode Power Limit 1

QUIET Mode Power Limit 1 Time Window

Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.

QUIET Mode Power Limit 2

QUIET Mode Platform PSYS PL1 Power

QUIET Mode Platform PL1 Time Window

Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default values. Indicates the time window over which Platform TDP value should be maintained.

QUIET Mode Platform PSYS PL2 Power

QUIET Mode IA ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

QUIET Mode GT ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

QUIET Mode Default Tcc

Power Saving Mode Power Limit 1

Power Saving Mode Power Limit 1 Time Window

Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.

Power Saving Mode Power Limit 2

Power Saving Mode Platform PSYS PL1 Power

Power Saving Mode Platform PL1 Time Window

Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default values. Indicates the time window over which Platform TDP value should be maintained.

Power Saving Mode Platform PSYS PL2 Power

Power Saving Mode IA ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Power Saving Mode GT ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Power Saving Mode Default Tcc

Performance Mode Power Limit 1

Performance Mode Power Limit 1 Time Window

Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.

Performance Mode Power Limit 2

Performance Mode Platform PSYS PL1 Power

Performance Mode Platform PL1 Time Window

Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default values. Indicates the time window over which Platform TDP value should be maintained.

Performance Mode Platform PSYS PL2 Power

Performance Mode IA ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Performance Mode GT ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Performance Mode Default Tcc

Entertainment Mode Power Limit 1

Entertainment Mode Power Limit 1 Time Window

Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.

Entertainment Mode Power Limit 2

Entertainment Mode Platform PSYS PL1 Power

Entertainment Mode Platform PL1 Time Window

Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default values. Indicates the time window over which Platform TDP value should be maintained.

Entertainment Mode Platform PSYS PL2 Power

Entertainment Mode IA ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Entertainment Mode GT ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Entertainment Mode Default Tcc

QUIET Mode Power Limit 1

QUIET Mode Power Limit 1 Time Window

Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.

QUIET Mode Power Limit 2

QUIET Mode Platform PSYS PL1 Power

QUIET Mode Platform PL1 Time Window

Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default values. Indicates the time window over which Platform TDP value should be maintained.

QUIET Mode Platform PSYS PL2 Power

QUIET Mode IA ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

QUIET Mode GT ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

QUIET Mode Default Tcc

Power Saving Mode Power Limit 1

Power Saving Mode Power Limit 1 Time Window

Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.

Power Saving Mode Power Limit 2

Power Saving Mode Platform PSYS PL1 Power

Power Saving Mode Platform PL1 Time Window

Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default values. Indicates the time window over which Platform TDP value should be maintained.

Power Saving Mode Platform PSYS PL2 Power

Power Saving Mode IA ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Power Saving Mode GT ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Power Saving Mode Default Tcc

Performance Mode Power Limit 1

Performance Mode Power Limit 1 Time Window

Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.

Performance Mode Power Limit 2

Performance Mode Platform PSYS PL1 Power

Performance Mode Platform PL1 Time Window

Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default values. Indicates the time window over which Platform TDP value should be maintained.

Performance Mode Platform PSYS PL2 Power

Performance Mode IA ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Performance Mode GT ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Performance Mode Default Tcc

Entertainment Mode Power Limit 1

Entertainment Mode Power Limit 1 Time Window

Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.

Entertainment Mode Power Limit 2

Entertainment Mode Platform PSYS PL1 Power

Entertainment Mode Platform PL1 Time Window

Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default values. Indicates the time window over which Platform TDP value should be maintained.

Entertainment Mode Platform PSYS PL2 Power

Entertainment Mode IA ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Entertainment Mode GT ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Entertainment Mode Default Tcc

QUIET Mode Power Limit 1

QUIET Mode Power Limit 1 Time Window

Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.

QUIET Mode Power Limit 2

QUIET Mode Platform PSYS PL1 Power

QUIET Mode Platform PL1 Time Window

Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default values. Indicates the time window over which Platform TDP value should be maintained.

QUIET Mode Platform PSYS PL2 Power

QUIET Mode IA ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

QUIET Mode GT ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

QUIET Mode Default Tcc

Power Saving Mode Power Limit 1

Power Saving Mode Power Limit 1 Time Window

Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.

Power Saving Mode Power Limit 2

Power Saving Mode Platform PSYS PL1 Power

Power Saving Mode Platform PL1 Time Window

Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default values. Indicates the time window over which Platform TDP value should be maintained.

Power Saving Mode Platform PSYS PL2 Power

Power Saving Mode IA ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Power Saving Mode GT ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Power Saving Mode Default Tcc

Performance Mode Power Limit 1

Performance Mode Power Limit 1 Time Window

Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.

Performance Mode Power Limit 2

Performance Mode Platform PSYS PL1 Power

Performance Mode Platform PL1 Time Window

Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default values. Indicates the time window over which Platform TDP value should be maintained.

Performance Mode Platform PSYS PL2 Power

Performance Mode IA ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Performance Mode GT ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Performance Mode Default Tcc

Entertainment Mode Power Limit 1

Entertainment Mode Power Limit 1 Time Window

Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.

Entertainment Mode Power Limit 2

Entertainment Mode Platform PSYS PL1 Power

Entertainment Mode Platform PL1 Time Window

Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default values. Indicates the time window over which Platform TDP value should be maintained.

Entertainment Mode Platform PSYS PL2 Power

Entertainment Mode IA ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Entertainment Mode GT ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Entertainment Mode Default Tcc

QUIET Mode Power Limit 1

QUIET Mode Power Limit 1 Time Window

Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.

QUIET Mode Power Limit 2

QUIET Mode Platform PSYS PL1 Power

QUIET Mode Platform PL1 Time Window

Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default values. Indicates the time window over which Platform TDP value should be maintained.

QUIET Mode Platform PSYS PL2 Power

QUIET Mode IA ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

QUIET Mode GT ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

QUIET Mode Default Tcc

Power Saving Mode Power Limit 1

Power Saving Mode Power Limit 1 Time Window

Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.

Power Saving Mode Power Limit 2

Power Saving Mode Platform PSYS PL1 Power

Power Saving Mode Platform PL1 Time Window

Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default values. Indicates the time window over which Platform TDP value should be maintained.

Power Saving Mode Platform PSYS PL2 Power

Power Saving Mode IA ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Power Saving Mode GT ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Power Saving Mode Default Tcc

Performance Mode Power Limit 1

Performance Mode Power Limit 1 Time Window

Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.

Performance Mode Power Limit 2

Performance Mode Platform PSYS PL1 Power

Performance Mode Platform PL1 Time Window

Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default values. Indicates the time window over which Platform TDP value should be maintained.

Performance Mode Platform PSYS PL2 Power

Performance Mode IA ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Performance Mode GT ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Performance Mode Default Tcc

Entertainment Mode Power Limit 1

Entertainment Mode Power Limit 1 Time Window

Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.

Entertainment Mode Power Limit 2

Entertainment Mode Platform PSYS PL1 Power

Entertainment Mode Platform PL1 Time Window

Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default values. Indicates the time window over which Platform TDP value should be maintained.

Entertainment Mode Platform PSYS PL2 Power

Entertainment Mode IA ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Entertainment Mode GT ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Entertainment Mode Default Tcc

QUIET Mode Power Limit 1

QUIET Mode Power Limit 1 Time Window

Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.

QUIET Mode Power Limit 2

QUIET Mode Platform PSYS PL1 Power

QUIET Mode Platform PL1 Time Window

Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default values. Indicates the time window over which Platform TDP value should be maintained.

QUIET Mode Platform PSYS PL2 Power

QUIET Mode IA ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

QUIET Mode GT ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

QUIET Mode Default Tcc

Power Saving Mode Power Limit 1

Power Saving Mode Power Limit 1 Time Window

Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.

Power Saving Mode Power Limit 2

Power Saving Mode Platform PSYS PL1 Power

Power Saving Mode Platform PL1 Time Window

Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default values. Indicates the time window over which Platform TDP value should be maintained.

Power Saving Mode Platform PSYS PL2 Power

Power Saving Mode IA ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Power Saving Mode GT ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Power Saving Mode Default Tcc

Performance Mode Power Limit 1

Performance Mode Power Limit 1 Time Window

Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.

Performance Mode Power Limit 2

Performance Mode Platform PSYS PL1 Power

Performance Mode Platform PL1 Time Window

Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default values. Indicates the time window over which Platform TDP value should be maintained.

Performance Mode Platform PSYS PL2 Power

Performance Mode IA ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Performance Mode GT ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Performance Mode Default Tcc

Entertainment Mode Power Limit 1

Entertainment Mode Power Limit 1 Time Window

Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.

Entertainment Mode Power Limit 2

Entertainment Mode Platform PSYS PL1 Power

Entertainment Mode Platform PL1 Time Window

Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default values. Indicates the time window over which Platform TDP value should be maintained.

Entertainment Mode Platform PSYS PL2 Power

Entertainment Mode IA ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Entertainment Mode GT ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Entertainment Mode Default Tcc

Power Limit 3

Platform PL1 Power

Platform PL2 Power

PSYS PMax Power

PSYS PMax power, defined in 1/8 Watt increments. Range 0-8192. For a PMax of 125W, enter 1000. 0 = AUTO. Uses BIOS VR mailbox command 0xB.

QUIET Mode Power Limit 1

QUIET Mode Power Limit 1 Time Window

Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.

QUIET Mode Power Limit 2

QUIET Mode Platform PSYS PL1 Power

QUIET Mode Platform PL1 Time Window

Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default values. Indicates the time window over which Platform TDP value should be maintained.

QUIET Mode Platform PSYS PL2 Power

QUIET Mode IA ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

QUIET Mode GT ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

QUIET Mode Default Tcc

Power Saving Mode Power Limit 1

Power Saving Mode Power Limit 1 Time Window

Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.

Power Saving Mode Power Limit 2

Power Saving Mode Platform PSYS PL1 Power

Power Saving Mode Platform PL1 Time Window

Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default values. Indicates the time window over which Platform TDP value should be maintained.

Power Saving Mode Platform PSYS PL2 Power

Power Saving Mode IA ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Power Saving Mode GT ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Power Saving Mode Default Tcc

Performance Mode Power Limit 1

Performance Mode Power Limit 1 Time Window

Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.

Performance Mode Power Limit 2

Performance Mode Platform PSYS PL1 Power

Performance Mode Platform PL1 Time Window

Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default values. Indicates the time window over which Platform TDP value should be maintained.

Performance Mode Platform PSYS PL2 Power

Performance Mode IA ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Performance Mode GT ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Performance Mode Default Tcc

Entertainment Mode Power Limit 1

Entertainment Mode Power Limit 1 Time Window

Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.

Entertainment Mode Power Limit 2

Entertainment Mode Platform PSYS PL1 Power

Entertainment Mode Platform PL1 Time Window

Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default values. Indicates the time window over which Platform TDP value should be maintained.

Entertainment Mode Platform PSYS PL2 Power

Entertainment Mode IA ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Entertainment Mode GT ICCMAX VALUE

ICCMAX , defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = Defulat.

Entertainment Mode Default Tcc

Advanced Chipset Control

Setup Menu Insyde Full Show

Setup Menu Insyde Full Show hide/show full menu item hide use for Tool change

Device Configuration

Show FlexiCharger

Show FlexiCharger Item

Start Charge

Start Range: 40%~95%

Stop Charge

Stop Range: 60%~100%

FlexiCharger

If you set the FlexiCharger to “Enabled”, note that over time the battery meter’ s reading accuracy will deteriorate.

Start Charge

Start Range: 40%~95%

Stop Charge

Stop Range: 60%~100%

MSHybrid or DISCRETE Switch

MSHybrid or DISCRETE Switch Control

MSHybrid Switch

MSHybrid or DISCRETE Switch Control

IGD or MSHybrid or DISCRETE Switch

IGD or MSHybrid or DISCRETE Switch Control

GPU Performance Scaling

Enabled or Disabled NV GPU Performance Scaling Support.

Intel(R) Speed Shift Technology

Enable/Disable Intel(R) Speed Shift Technology support. Enabling will expose the CPPC v2 interface to allow for hardware controlled P-states.

VT-d

Check to enable VT-d function on MCH.

UEFI OS Fast Boot

If enabled the system firmware does not initialize keyboard and check for firmware menu key.

Execute Disable Bit

XD can prevent certain classes of malicious buffer overflow attacks when combined with a supporting OS (Windows Server 2003 SP1, Windows XP SP2, SuSE Linux 9.2, RedHat Enterprise 3 Update 3.)

ME State

When Disabled ME will be put into ME Temporarily Disabled Mode.

HYPER PERFORMANCE

HYPER PERFORMANCE SWITCH POWER MODE FUNCTION.

USB Boot

Disables or enables booting to USB boot devices.

CD-ROM Boot

Disables or enables booting to CD-ROM boot devices.

AC Fan Control

AC Fan Control or not

Boot Keyboard Backlight Mode

Keyboard Backlight Mode Enable/Disable.

Boot Keyboard Backlight Brightness Level

Customized change keyboard brightness level.

Colorful Keyboard Effects Mode

Customized change keyboard color effects.

Colorful Keyboard Color Mode

Customized change keyboard Color.

USB TYPE C PORT 1 CONTROL

USB TYPE C PORT 1 Enable/Disable Port

USB TYPE C PORT 2 CONTROL

USB TYPE C PORT 2 Enable/Disable Port

USB 3.0 PORT 1 CONTROL

USB 3.0 PORT 1 Enable/Disable Port

USB 3.0 PORT 2 CONTROL

USB 3.0 PORT 2 Enable/Disable Port

WEBCAM Device Control

WEBCAM Device Enable/Disable

BLUETOOTH Device Control

BLUETOOTH Device Enable/Disable

3G OR 4G CARD Control

3G OR 4G CARD Enable/Disable

WLAN Device Control

WLAN Device Enable/Disable

FINGER PRINTER Device Control

FINGER PRINTER Device Enable/Disable

Audio Device Control

Audio Device Enable/Disable

Wake On Lan

Wake On Lan Enable/Disable

Glan Device Control

Glan Device Enable/Disable

Cardreader Device Control

Cardreader Device Enable/Disable

Microphone Control

Microphone Enable/Disable(only supoort DMIC)

Set WMI Battery Saver function support

Enable/Disable Battery Saver

Battery Saver

Enable/Disable Battery Saver

Power Gating function

Current TPM Device

Current TPM Device: TPM1.2, or TPM2.0.

TPM Operation

Enable/Disable TPM Function. This option will automatically return to No-Operation.

TPM Active PCR Hash Algorithm

TPM Hardware Supported Hash Algorithm

BIOS Supported Hash Algorithm

TrEE Protocol Version

TrEE Protocol Version: 1.0 or 1.1

PCR Bank: SHA1 Enabled

TCG2 Request PCR Bank: SHA1

PCR Bank: SHA256 Enabled

TCG2 Request PCR Bank: SHA256

PCR Bank: SHA384 Enabled

TCG2 Request PCR Bank: SHA384

PCR Bank: SHA512 Enabled

TCG2 Request PCR Bank: SHA512

PCR Bank: SM3_256 Enabled

TCG2 Request PCR Bank: SM3_256

Enabled

Supervisor Password Not Installed

User Password Not Installed

User Access Level

Set Supervisor Password

Old password

Please input old password to make chage work

New Password

Install or Change the password and the length of password must be greater than one character.

Confirm Password

Set User Password

Old password

Please input old password to make chage work

New Password

Install or Change the password and the length of password must be greater than one character.

Confirm Password

Clear User Password

Power on Password

Enable:System will ask input password on post time. Disable:System will ask input password when go to Setup Utility

TPM Configuration

Set All Hdd Password

Old password

Please input old password to make chage work

New Password

Confirm Password

Set All Master Hdd Password

Old password

Please input old password to make chage work

New Password

Confirm Password

Storage Password Setup Page

Security Device Support

Enable or disable BIOS Support for TPM 2.0 security device. TPM 2.0 is only supported if UEFI Boot is Enabled. The O.S. will not show the Security Device. TCG EFI protocol and INT1A Interface will not be available.

Security Device Support

Clear TPM Enabled

Clear TPM. Removes all TPM context associated with a specific Owner.

TPM20 Device Found

Current BlockSID Status:

BlockSID is enabled

BlockSID is disabled

Require physical presence when enable BlockSID

Not require physical presence when enable BlockSID

Require physical presence when disable BlockSID

Not require physical presence when disable BlockSID

TCG Storage Action

Change BlockSID actions, includes enable or disable BlockSID, Require or not require physical presence when remote enable or disable BlockSID

Device List

↑ and ↓ to change option, ENTER to select an option, ESC to exit

Device Name: [Not Installed]

Security Mode: Uninstall

ACPI S1

Enable/Disable ACPI S1/S3 Sleep state

ACPI S3

Enable/Disable ACPI S1/S3 Sleep state

Wake on PME

Determines the action taken when the system power is off and a PCI Power Management Enable wake up event occurs.

Wake on Modem Ring

Determines the action taken when the system power is off and a modem connected to the serial port is ringing.

Auto Wake on S5

Auto wake on S5, By Day of Month or Fixed time of every day

Wake on S5 Time

This is the help for the hour, minute, second field. Valid range is from 0 to 23, 0 to 59, 0 to 59. INCREASE/REDUCE : +/-.

Day of Month

This is the help for the day field. Valid range is from 1 to 31. (Error checking will be done against month/day/year combinations that are not suppo-ported. INCREASE/REDUCE : +/-.

S5 Long Run Test

Enable : force to enable RTC S5 wake up, even if OS disables it. Support ipwrtest to do RTC S5 wakeup.

H2OUve Configuration

Quick Boot

Allows InsydeH2O to skip certain tests while booting. This will decrease the time needed to boot the system.

Quiet Boot

Disables or enables booting in Text Mode.

Power Up In Standby Support

Storage PCI Option Rom access right Support

Disable or enable storage PCI option rom acceess right. This feature will enable or disable storage PCI option rom being load and dispatched.

Add Boot Options

Position in Boot Order for Shell,Network and Removables

ACPI Selection

Select booting to Acpi3.0/Acpi4.0/Acpi5.0/Acpi6.0/Acpi6.1/Acpi6.2/Acpi6.3

EFI Device First

Determine EFI device first or legacy device first. If enable, it is EFI device first. If disable, it is Legacy device first.

USB Hot Key Support

Enable/Disable to support USB hot key while booting. This will decrease the time needed to boot the system.

Timeout

The number of seconds that the firmware will wait before booting the original default boot selection.

Automatic Failover

Enable: if boot to default device fail, it will directly try to boot next device. Disable: if boot to default device fail, it will pop warning message then go into firmware UI.

EFI

Legacy

UEFI Setting

Boot Type

Select boot type to Dual type, Legacy type or UEFI type

Network Stack

Network Stack Support: Windows 8 BitLocker Unlock UEFI IPv4/IPv6 PXE Legacy PXE OPROM

PXE Boot to LAN

Disables or enables PXE boot to LAN.

PXE Boot capability

Disabled : Support Network Stack UEFI PXE : IPv4/IPv6 Legacy : Legacy PXE OPROM only

EFI

Boot Device Priority

Normal Boot Menu

Select Normal Boot Option Priority or Advance Boot Option Priority

Boot Type Order

Floppy Drive

Hard Disk Drive

CD/DVD-ROM Drive

PCMCIA

USB

EMBED NETWORK

BEV

Others

Boot Type Order

Hard Disk Drive

CD/DVD-ROM Drive

Floppy Drive

Others

PCMCIA

USB

EMBED NETWORK

BEV

Exit Saving Changes

Exit system setup and save your changes.

Save Change Without Exit

Save your changes and without exiting system.

Exit Discarding Changes

Exit system setup and without saving your changes.

Discard Changes

H2OUve Setup

H2OUVE Support

Enable/Disable interface of settings of SCU for H2OUVE tool.